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研究生:沈稚鈞
研究生(外文):Chih-Chun Shen
論文名稱:使用砷化鎵異質接面雙載子電晶體和高電子遷移率電晶體技術之微波疊接功率放大器研究
論文名稱(外文):Research on Microwave Stacked Power Amplifiers using GaAs HBT and HEMT Technologies
指導教授:張鴻埜
指導教授(外文):Hong-Yeh Chang
學位類別:博士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:129
中文關鍵詞:功率放大器堆疊式功率放大器雙閘極電晶體
外文關鍵詞:power amplifierstacked power amplifierdual-gate transistor
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本篇論文研究主題為疊接式功率放大器設計與雙閘極功率放大器設計,疊接式功率放大器電路同時使用砷化鎵(GaAs)基板之異質接面雙載子電晶體(HBT)與高電子遷移率電晶體(HEMT)組合而成,包含完整的分析模擬與實驗結果,經由探討兩層疊接式功率放大器之最佳組合,進一步討論至三層疊接式功率放大器之最佳組合,論文中分析了不同方式的疊接架構(HEMT-HBT, HBT-HEMT, HBT-HBT, 與 HEMT-HEMT疊接架構),分析最佳的兩層疊接架構方式而得到較大的輸出阻抗,進而提升最大輸出功率以及寬頻的特性,此單晶片單級兩層疊接式功率放大器具有操作頻率由3.5至6.5 GHz增益大於13 dB,P1dB大於26.4 dBm,效率可達38%特性,並以兩層疊接式架構為基礎,探討三層疊接架構中之第三層疊接電晶體對於整體三層疊接式功率放大器電路的增益、頻寬以及輸出功率特性的影響,並有效提升三層疊接式功率放大器電路的輸出功率與效率特性,此單晶片單級三層疊接式功率放大器具有操作頻率由3.1至5.8 GHz增益大於15 dB,P1dB大於29.5 dBm,最大效率可達38.3%特性。
雙閘極功率放大器使用砷化鎵(GaAs)基板之高電子遷移率電晶體(HEMT)組合而成,雙閘極電晶體佈局中的汲極(Drain)端與源極(Source)端之間有兩個閘極(Gate)控制通道特性,基於小訊號萃取技術得到雙閘極電晶體等校電路模型,並根據疊接式功率放大器設計分析方式,設計並分析使用雙閘級高電子遷移率電晶體功率放大器,分析兩種不同架構(空乏-空乏型D-D mode, 與增強-增強型E-E mode)之雙閘極功率放大器,使用E-E mode雙閘極電晶體架構設計之功率放大器具有較大的1-dB輸出功率壓縮點,較好的線性度與寬頻特性,此單晶片單級雙閘極功率放大器具有操作頻率由3.6至8 GHz增益大於12 dB,P1dB大於26.8 dBm,最大效率可達29.7%特性。
本論文藉由疊接式功率放大器設計方式,成功設計了兩層疊接式功率放大器、三層疊接式功率放大器與雙閘極功率放大器,其中分析了疊接式電晶體設計對於頻寬的影響以及設計於雙閘極功率放大器得到較好的線性度特性,未來可進一步應用於新世代無線通訊功率放大器。
Research on the stacked power amplifiers (PAs) and dual-gate PAs in microwave are presented in this dissertation. The stacked power amplifier circuits are designed using several heterojunction bipolar transistor (HBT) and high electron mobility transistor (HEMT) process. The analysis and simulation is agreed well with experimental results. By investigated the best combination of transistors in dual stacked power amplifier, the best stacked transistor of triple stacked power amplifiers is analyzed. Different stacked architectures (HEMT-HBT, HBT-HEMT, HBT-HBT, and HEMT-HEMT stacking architectures) are analyzed, and the optimal dual stacked architecture is analyzed to obtain larger output impedance, enhancement in the maximum output power, and broad bandwidth characteristics. The single-chip single-stage dual stacked power amplifier achieves an operating frequency from 3.5 to 6.5 GHz with a gain of more than 13 dB, an output 1-dB compression point (P1dB) of higher than 26.4 dBm, and an efficiency of up to 38%. Base on the architecture of the proposed dual stacked PA, the third-stacked transistor in the triple stacked PA is analyzed and realized with an enhancement of gain, bandwidth and output power performance. The single-chip single-stage triple-stacked power amplifier achieves an operating frequency from 3.1 to 5.8 GHz with a gain of more than 15 dB, a P1dB of higher than 29.5 dBm, and a maximum efficiency of up to 38.3%.
The dual-gate power amplifier is realized by a GaAs HEMT process. There are two gates between the drain and source terminal in one transistor. The channel is controlled by two gates in different operation mode. The equivalent model of dual-gate transistor is obtained from the small signal extraction. By using of the equivalent model and the design methodology of stacked PA, two dual-gate PAs are designed and realized. According to the design and analysis of dual-gate PA, two different architectures (depletion-depletion D-D mode, and enhancement-enhancement E-E mode) are realized. The dual-gate E-E mode PA exhibits a larger output P1dB, a good linearity and broad bandwidth characteristics. The single-chip single-stage dual-gate power amplifier achieves an operating frequency from 3.6 to 8 GHz with a gain of more than 12 dB, a P1dB greater than 26.8 dBm, and a maximum efficiency of up to 29.7%.
Dual stacked PAs, triple stacked PAs and dual-gate PAs are successfully designed and analyzed in this dissertation. The bandwidth characteristic is analyzed by the stacked transistor. According to the design methodology of the stacked PA, the dual-gate PAs are designed and analyzed with good linearity characteristic. It can be further utilized to the new generation wireless communication PA and modern mobile application due to its good circuit performance and the mass-production MMIC process.
摘要 I
Abstract III
誌謝 V
Table of Contents VII
List of Figures IX
List of Tables XV
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Literatures survey 2
1.3 Contributions 10
1.4 Dissertation Organization 11
Chapter 2 Dual-stacked power amplifier in GaAs BiHEMT process 13
2.1 Introduction 13
2.2 Designed MMIC Process 14
2.3 GaAs 0.5m/ 2m BiHEMT common-emitter and common-gate stacked power amplifier 15
2.3.1 MMIC process 15
2.3.2 Design and analysis 15
2.3.3 Experimental results 27
2.4 Summary 32

Chapter 3 Triple-stacked power amplifiers in GaAs BiHEMT process 33
3.1 Introduction 33
3.2 Designed MMIC Process 34
3.3 GaAs 0.5m/ 2m BiHEMT triple-stacked power amplifiers 35
3.3.1 MMIC process 35
3.3.2 Design and analysis 35
3.3.3 Experimental results 44
3.4 Summary 50
Chapter 4 Dual-gate power amplifiers in GaAs PHEMT process 53
4.1 Introduction 53
4.2 Designed MMIC Process 54
4.3 AlGaAs/GaAs 0.5m E/D-mode PHEMT dual-gate power amplifiers 55
4.3.1 MMIC process 55
4.3.2 Design and analysis 55
4.3.3 Experimental results 73
4.4 Summary 96
Chapter 5 Conclusions 97
Bibliography 99
Publication List 105
[1] M. Jaber, M. A. Imran, R. Tafazolli, and A. Tukmanov, “ 5G backhaul challenges and emerging research directions: A survey,” IEEE Access, vol. 4, pp. 1743-1766, Apr. 2016.
[2] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, “A watt-level stacked-FET linear power amplifier in silicon-on-insulator CMOS,” IEEE Trans. Microw. Theory Tech., vol. 58, pp.57-64, Jan. 2010.
[3] J. Jeong, S. Pornpromlikit, P. M. Asbeck, and D. Kelly, “A 20 dBm linear RF power amplifier using stacked silicon-on sapphire MOSFETs,” IEEE Microw. and Wireless Compon. Lett., pp. 684-686, Dec. 2006.
[4] M. Fathi, D. K. Su, and B. A. Wooley, “A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1-4.
[5] S. Leuschner, J.-E. Mueller, and H. Klar, “A 1.8 GHz wide-band stacked-cascode CMOS power amplifier for WCDMA application in 65 nm standard CMOS,” in IEEE Radio Freq. Integrated Circuit Symp. Dig., 2011, pp. 1-4.
[6] S. Pornpromlikit, H.-T. Dabag, B. Hanafi, J. Kim, L. E. Larson, J. F. Buckwalter, and P. M. Asbeck, “A Q-band amplifier implemented with stacked 45-nm CMOS FETs,” in IEEE Compound Semicond. Integr. Citcuit Symp. Dig., 2011, pp. 1-4.
[7] Z.-M. Tsai, M.-F. Lei, and H. Wang, “An HBT four-cell monolithic stacked power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., June 2007, pp. 151-154.
[8] H.-Y. Chang, Y.-C. Liu, S.-H. Weng, C.-H. Lin, Y.-L. Yeh, and Y.-C. Wang, “Design and analysis of a DC-43.5-GHz fully integrated distributed amplifier using GaAs HEMT-HBT cascode gain stage,” IEEE Trans. Microw. Theory Tech., vol. 59, pp.443-455, Feb. 2011.
[9] C.-H. Lin, and H.-Y. Chang, “A high efficiency broadband class-E power amplifier using a reactance compensation technique,” IEEE Microw. and Wireless Compon. Lett., vol. 20, no. 09, pp. 507-509, Sept. 2010.
[10] A. K. Ezzeddine, and H. C. Huang, “The high voltage/high power FET(HiVP),” in IEEE Radio Frequency Integrated Circuits Symp. Dig., June 2003, pp, 215-218.
[11] C.-C. Shen, F.-H. Huang, C.-K. Lin, H.-Y. Chang, Y.-J. Chan, and Y.-C. Wang, “A broadband stacked power amplifier using 2-µm GaAs HBT process for C-band applications,” in 2008 Asia Pacific Microw. Conf. Proc., Dec. 2008, pp. 1-4.
[12] D. Fritsche, R. Wolf, and F. Ellinger, “Analysis and design of a stacked power amplifier with very high bandwidth,” IEEE Trans. Microw. Theory and Tech., vol. 60, pp. 3223-3231, Oct. 2012.
[13] K. Datta, J. Roderick, and H. Hashemi, “A triple-stacked class-E mm-wave SiGe HBT power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., June 2013, pp. 1-3.
[14] C. Liu, Q. Li, Y. Li, X. Li, H. Liu, and Y.-Z. Xiong, “An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips,” in 41st ESSCIRC, Sept. 2015, pp. 68-71.
[15] M. Squartecchia, T. K. Johansen, and V. Midili, “Design procedure for millimeter-wave InP DHBT stacked power amplifiers,” in 2015 INMMiC, Oct. 2015, pp. 1-3.
[16] K. Datta, and H. Hashemi, “Performance limits, design and implementation of mm-Wave SiGe HBT class-E and stacked class-E power amplifiers,” IEEE J. Solid-State Circuit, vol. 49, no. 10, pp. 2150-2171, Oct. 2014.
[17] S. M. A. Ali, and S. M. R. Hasan, “A 38-GHz millimeter-wave double-stacked HBT class-F⁻¹ high-gain power amplifier in 130-nm SiGe-BiCMOS,” IEEE Trans. Microw. Theory Tech., pp. 1-6, May 2020.
[18] K. W. Kobayashi, and Y. Z. McCleary, “Baseband to 140-GHz SiGe HBT and 100-GHz InP DHBT broadband triple-Stacked distributed amplifiers with active bias terminations,” IEEE J. Solid-State Circuit, pp. 1-9, May 2020.
[19] J.-H. Chen, S. R. Helmi, R. Azadegan, F. Aryanfar, and S. Mohammadi, “A broadband stacked power amplifier in 45-nm CMOS SOI technology,” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 2775-2784, Aug. 2013.
[20] J.-H. Chen, S. R. Helmi, A. Y.-S. Jou, and S. Mohammadi, “A wideband power amplifier in 45 nm CMOS SOI technology for X band applications,” IEEE Microw. Compon. Lett., vol. 23, no. 11, pp. 587-589, Sept. 2013.
[21] H.-T. Dabag, B. Hanafi, F. Golcuk, A. Agah, J. F. Buckwalter, and P. M. Asbeck, “Analysis and design of stacked-FET millimeter-wave power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1543-1556, Mar. 2013.
[22] A. Chakrabarti, and H. Krishnaswamy, “High-power high-efficiency class-E-like stacked mmWave PAs in SOI and Bulk CMOS: theory and implementation,” IEEE Trans. Microw. Theory Tech., vol. 62, no. 8, pp. 1686-1704, June 2014.
[23] M. Fathi, D. K. Su, and B. A. Wooley, “A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., Sept. 2010, pp. 1-4.
[24] H.-F. Wu, Q.-F. Cheng, X.-G. Li, and H.-P. Fu, “Analysis and design of an ultrabroadband stacked power amplifier in CMOS Technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 1, pp. 49-53, Jan. 2016.
[25] J. P. Aikio, M. Hietanen, N. Tervo, T. Rahkonen, and A. Parssinen, “Ka-Band 3-stack power amplifier with 18.8 dBm Psat and 23.4 % PAE using 22nm CMOS FDSOI Technology,” in IEEE Topical Conf. on RF/Microw. Power Amp. for Radio and Wireless, Jan. 2019, pp. 1-3.
[26] Y. Chang, B.-Z. Lu, Y. Wang, and H. Wang, “A Ka-band stacked power amplifier with 24.8-dBm output power and 24.3% PAE in 65-nm CMOS Technology,” in IEEE MTT-S Inter. Microw. Symp. Dig., June 2019, pp. 316-319.
[27] H. Wu, X. Liao, C. Wang, Y. Chen, Y. Hua, L. Hu, J. Lv, and W. Tong, “A 4-10 GHz fully-integrated stacked GaAs pHEMT power amplifier,” in IEEE MTT-S Inter. Microw. Symp., June 2017, pp. 24-26.
[28] C. Lee, Y. Kim, Y. Koh, J. Kim, K. Seo, J. Jeong, and Y. Kwon, “A 18 GHz broadband stacked FET power amplifier Using 130 nm metamorphic HEMTs,” IEEE Microw. Compon. Lett., vol. 19, no. 12, pp. 828-830, Dec. 2009.
[29] M. Gavell, I. Angelov, M. Ferndahl, and H. Zirath, “A high voltage mm-wave stacked HEMT power amplifier in 0.1 µm InGaAs technology,” in IEEE MTT-S Inter. Microw. Symp., May 2015, pp. 1-3.
[30] F. Thome, and O. Ambacher, “A 50-nm gate-length metamorphic HEMT distributed power amplifier MMIC based on stacked-HEMT unit cells,” in IEEE MTT-S Inter. Microw. Symp., June 2017, pp. 1695-1698.
[31] C.-C. Shen, H.-Y. Chang, and Y.-C. Wang, “A monolithic 3.5-to-6.5 GHz GaAs HBT-HEMT/common-emitter and common-gate stacked power amplifier,” IEEE Microw. Compon. Lett., vol. 22, no. 9, pp. 474-476, Sept. 2012.
[32] G.-Y. Chen, H.-Y. Chang, S.-H. Weng, C.-C. Shen, Y.-L. Yeh, J.-S. Fu, Y.-M. Hsin, and Y.-C. Wang, “Dseign and analysis of a Ka-band monolithic high efficiency frequency quadrupler using GaAs HBT-HEMT common-base/common-source balance topology,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 10, pp. 3674-3689, Oct. 2013.
[33] S.-H. Chen, Y.-C. Liu, S.-H. Weng, H.-Y. Chang, K. Chen, and S.-H. Wu, “A monolithic DC–31 GHz distributed amplifier using cascode HBT-NMOS gain cell in 0.18 μm SiGe technology,” in 2012 Asia Pacific Microw. Conf. Proc., Dec. 2012, pp. 211-213.
[34] G.-Y. Chen, H.-Y. Chang, S.-H. Weng, Y.-M. Hsin, and Y.-C. Wang, “2.8 dB conversion gain broadband HBT-HEMT balanced frequency tripler with high harmonic suppression,” Electron. Lett., vol. 50, no.11, pp. 812-814, June 2014.
[35] C.-H. Lu, C.-H. Lin, Y.-H. Liao, H.-Y. Chang, and Y.-C. Wang, “Monolithic 2-μm/0.5-μm GaAs HBT-HEMT (BiHEMT) process for low phase noise voltage controlled oscillators (VCOs),” in 2012 Asia Pacific Microw. Conf. Proc., Dec. 2012, pp. 1235-1237.
[36] X. Xia, X. Cheng, F. Chen, X. Luo, and X. Deng, “An improved colpitts VCO with low phase noise using a GaAs BiHEMT process,” IEEE Microw. Compon. Lett., vol. 30, no. 1, pp. 70-73, Jan. 2020.
[37] K. W. Kobayashi, D. K. Umemoto, T. R. Block, A. K. Oki, and D. C. Streit, “A monolithically integrated HEMT–HBT low noise high linearity variable gain amplifier,” IEEE J. Solid-State Circuit, vol. 31, no. 5, pp. 714-718, May 1996.
[38] C. Tsironis, and R. Meierer, “Microwave wide-band model of GaAs dual gate MESFET’s,” IEEE Trans. Microw. Theory Techn., vol. MTT-30, no. 3, pp. 243-251, Mar. 1982.
[39] W. R. Deal, M. Biedenbender, P.-H. Liu, J. Uyeda, M. Siddiqui, and R. Lai, “Design and analysis of broadband dual-gate balanced low-noise amplifiers,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2107-2115, Oct. 2007.
[40] S. E. Shih, W. R. Deal, D. M. Yamauchi, W. E. Sutton, W. B. Luo, Y. Chen, I. P. Smorchkova, B. Heying, M. Wojtowicz, and M. Siddiqui, “Design and analysis of ultra wideband GaN dual-gate HEMT low-noise amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, Dec. 2009.
[41] R. Quay, A. Tessmann, R. Kiefer, S. Maroldt, C. Haupt, U. Nowotny, R. Weber, H. Massler, D. Schwantuschke, M. Seelmann-Eggebert, A. Leuther, and M. Mikulla, O. Ambacher, “Dual-gate GaN MMICs for MM-wave operation,” IEEE Microw. Compon. Lett., vol.21 ,no.2 , pp. 95-97, Feb. 2011.
[42] D. Schwantusche, C. Haupt, R. Kiefer, P. Brückner, M. Seelmann-Eggebert, M. Mikulla, I. Kallfass, and R. Quay, “A 56-65 GHz high-power amplifier MMIC using 100 nm AlGaN/GaN dual-gate HEMTs,” in Proc. 5th Eur. Microw. Integrated Conf. (EuMIC11), Manchester, UK, Oct. 2011, pp. 656-659.
[43] D.-M. Lin, C.-K. Lin, F.-H. Huang, J.-S. Sutton, W.-K. Wang, Y.-Y. Tsai, Y.-J. Chan, and Y.-C. Wang, “Dual-gate E/E- and E/D-mode AlGaAs/InGaAs pHEMTs for microwave circuit applications,” IEEE Trans. Electron Device, vol. 54, no. 8, Aug. 2007.
[44] A. Tessmann, W. H. Haydl, M. Neumann, S. Kudszus, and A. Hülsmann, “A coplanar W-band power amplifier MMIC using dual-gate HEMTs,” in Proc. 29th Eur. Microw. Conf. (EuMC99), Oct. 1999, pp. 246-249.
[45] H.-Y. Chang, and K.-H. Liang, “A 0.18-m dual-gate CMOS device modeling and applications for RF cascode circuits,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 1, Jan. 2011.
[46] H.-Y. Chang, C.-H. Lin, Y.-C. Liu, Y.-L. Yeh, K. Chen, and S.-H. Wu, “65 nm CMOS dual-gate device for Ka-band broadband low noise amplifier and high-accuracy quadrature voltage controlled oscillator,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 6, pp. 2402-2413, Jun. 2013.
[47] D. Langrez, E. Delos, and G. Salmer, “Modelling of 0.15-m dual gate PM-HEMTs by using experimental extraction,” in Proc. Eur. Microw. Conf. (EuMC), 1994, pp. 355-360.
[48] J. R. Scott, and R. A. Minasian, “A simplified microwave model of the GaAs dual-gate MESFET,” IEEE Trans. Microw. Theory Techn., vol. MTT-32, no. 3, pp. 243-248, Mar. 1984.
[49] C.-C. Shen, H.-Y. Chang, and G. D. Vendelin, “Comparison of enhancement- and depletion-mode triple stacked power amplifiers in 0.5-m AlGaAs/GaAs PHEMT technology,” in Proc. 4th Eur. Microw. Integrated Conf. (EuMIC09), Rome, Italy, Sep. 2009, pp. 222-225.
[50] N. B. D. Carvalho, and J. C. Pedro, “Large- and small-signal IMD behavior of microwave power amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 47, no. 12, pp. 2362-2374, Dec. 1999.
[51] C. Fager, J. C. Pedro, N. B. D. Carvalho, H. Zirath, F. Fortes, and M. J. Rosário, “A comprehensive analysis of IMD behavior in RF CMOS power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 24-34, Jan. 2004.
[52] H.-K. Lin, C.-L. Chao, M.-C. Tu, T.-C. Tsai, and Y.-C. Wang, “Structure and a method for monolithic integration of HBT, depletion-mode HEMT and enhancement-mode HEMT on the same substrate,” U.S. Patent 0 278 523, Dec. 6, 2007.
[53] R. Santhakumar, B. Thibeault, M. Higashiwaki, S. Keller, Z. Chen, U. K. Mishra, and R. A. York, “Two-stage high-gain high-power distributed amplifier using dual-gate GaN HEMTs,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 8, pp. 2059-2063, Aug. 2011.
[54] P. Dennler, R. Quay, P. Br¨uckner, M. Schlechtweg, and O. Ambacher, “Watt-level non-uniform distributed 6–37 GHz power amplifier MMIC with dual-gate driver stage in GaN technology,” in IEEE Topical Conf. on RF/Microw. Power Amp. for Radio and Wireless, Jan. 2014, pp. 37-39.
[55] H. Yao, Y. Cao, X. Wang, Y. Zhong, and Z. Jin, “W-band MMIC amplifiers based on 50-nm dual-gate InP HEMT,” in Proc. 5th Global Symp. On Millimeter-Waves (GSMM12), May 2012, pp. 9-13.

[56] S.-H. Chen, C.-C. Shen, S.-H. Weng, Y.-C. Liu, H.-Y. Chang, and Y.-C. Wang, “Design og A DC-33 GHz Cascode Distributed Amplifier using Dual-gate Device in 0.5-um FaAs E/D-Mode HEMT Process,” in 2013 Asia Pacific Microwave Conf. Proc., Nov. 2013, pp. 728-730.
[57] P. Dennler, F. V. Raay, M. Seelmann-Eggebert, R. Quay, and O. Ambacher, “Modeling and realization of GaN-Based dual-gate HEMTs and HPA MMICs for Ku-band applications,” in IEEE MTT-S Inter. Microw. Symp., June 2011, pp.1-4.
[58] G. Lasser, M. R. Duffy, and Z. Popovi´c, “Dynamic dual-gate bias modulation for linearization of a high-efficiency multistage PA,” IEEE Trans. Microw. Theory Techn., vol. 67, no. 7, pp. 2483-2494, July. 2019.
[59] S. Heck, S. Maroldt, A. Br¨ackle, M. Berroth, R. Quay, “Comparison of a single and a dual-gate GaN switching-amplifier for future communication systems,” in IEEE MTT-S Inter. Microw. Symp., June 2011, pp.1-4.
[60] Y. C. Li, F.-H. Huang, and Q. Xue, “20-40 GHz dual-gate frequency doubler using 0.5 μm GaAs pHEMT technology,” Electron. Lett., vol. 50, no.10, pp. 758-759, June 2014.
[61] F.-H. Huang, M.-H. Tsai, H.-Y. Chang, and Y.-M. Hsin, “A dual-gate subharmonic injection-locked oscillator using 0.5-m GaAs pHEMT Technology,” in 2012 Asia Pacific Microw. Conf. Proc., Dec. 2010, pp. 940-943.
[62] H. Umeda, Y. Yamada, K. Asanuma, F. Kusama, Y. Kinoshita, H. Ueno, H. Ishida, T. Hatsuda, and T. Ueda, “High power 3-phase to 3-phase matrix converter using Dual-gate GaN bidirectional switches,” in 2018 IEEE Applied Power Electro. Conf., Mar. 2018, pp. 894-897.
[63] Q. Li, W. Che, H. Chen, L. Gu, and W. Feng, “Dual-gate GaN-HEMT SPDT switch with high isolation,” in 2014 IEEE International Conf. Communication Problem-solving., Dec. 2014, pp. 134-137.
[64] M. Guacci, D. Zhang, M. Tatic, D. Bortis, J. W. Kolar, Y. Kinoshita, and H. Ishida, “Three-phase two-third-PWM buck-boost current source inverter system employing dual-gate monolithic bidirectional GaN e-FETs,” CPSS Transactions on Power Electroics and Applications, vol. 4, no. 4, pp. 339-354, Dec. 2019.
[65] C. M. Grotsch, S. Wagner, L. John, I. Kallfass, “A dual-gate downconverter for H-band employing an active load,” in 2019 IEEE International Conf. on Microw. Antennas Communications and Electronic Systems (COMCAS), Nov. 2019, pp. 1-5.
[66] J. S. Moon, R. Grabar, D. Brown, I. Alvarado-Rodriguez, D. Wong, A. Schmitz, H. Fung, P. Chen, J.-C. Kang, S. Kim, T. Oh, and C. Mcguire, “>70% Power-added-efficiency dual-gate, cascode GaN HEMTs without harmonic tuning,” IEEE Electron Device Lett., vol. 37, no. 3, pp. 272-275, Mar. 2016.
[67] W. J. Ho, M. F. Chang, S. M. Beccue, P. J. Zampardi, J. Yu, A. Sailer, R. L. Pierson, and K. C. Wang, “A GaAs BiFET LSI technology,” in IEEE GaAs IC Symp. Dig., Oct. 1994, pp. 47–50.
[68] H.Wang, R. Lai, L. Tran, J. Cowles, Y. C. Chen, E. W. Lin, H. H. Liao, M. K. Ke, T. Block, and H. C. Yen, “A single-chip 94 GHz frequency source using InP-based HEMT–HBT integration technology,” in IEEE RFIC Symp. Dig., Jun. 1998, pp. 275–278.
[69] D. C. Streit, D. K. Umemoto, K. W. Kobayashi, and A. K. Oki, “Monolithic HEMT-HBT integration by selective MBE,” IEEE Trans. Electron Devices, vol. 42, no. 4, pp. 618–623, Apr. 1995.
[70] S.-H. Weng, H.-Y. Chang, C.-C. Chiong, and Y.-C. Wang, “Gain-bandwidth analysis of broadband darlington amplifiers in HBT-HEMT process,” IEEE Trans. Microw. Theory and Techn., vol. 60, no. 11, pp. 3458-3473, Nov. 2012.
[71] W. E. Stanchina, J. J. Brown, M. Hafizi, R. H. Walden, H. C. Sun, and M. Rodwell, “InP-based mixed signal/mixed device technology,” in Int. GaAs Manuf. Technol. Conf. Dig., 1996, pp. 160–163.
[72] H. Shin, J.-H. Son, and Y.-S. Kwon, “Monolithic integration of AlGaAs/GaAs HBT and GaAs junction-gate floated electron channel field effect transistor using selective MOCVD growth,” IEEE Microw. Guided Wave Lett., vol. 6, no. 8, pp. 317–319, Aug. 1996
[73] A. G. Metzger, R. Ramanathan, J. Li, H.-C. Sun, C. Cismaru, H. Shao, L. Rushing, K. P. W. , C.-J. Wei, Y. Zhu, A. Klimashov, Y. A. Tkachenko, B. Li, and P. J. Zampardi, “An InGaP/GaAs merged HBT-FET (BiFET) technology and applications to the design of handset power amplifiers,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2137–2148, Oct. 2007.
[74] K. W. Kobayashi, D. C. Streit, A. K. Oki, D. K. Umemoto, and T. R. Block, “A novel monolithic linearized HEMT LNA using HBT tunable active feedback,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1996, pp. 1217–1220.
[75] S. J. Mason, “Power gain in feedback amplifiers,” IRE Trans. Circuits Theory, vol. CT-1, no. 2, pp. 20–25, June 1954.
[76] “Agilent 85190A IC-CAP 2008,” Agilent Technologies, Santa Clara, CA, 2008
[77] L. Yang, and S. I. Long, “New method to measure the source and drain resistance of the GaAs MESFET,” IEEE Electron Device Lett., vol. EDL-7, no. 2, pp. 75–77, Feb. 1986.
[78] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A new method for determining the FET small-signal equivalent circuit,” IEEE Trans. Microw. Theory and Techn., vol. 36, no. 7, pp. 1151–1159, July. 1988.
[79] Datasheet of CREE CMPA2560025D.
(http://www.dz863.com/datasheet-8387020763-CMPA2560025D_Cree-5w-Gan-Hemt-Mmic-Cree-Wireless-Driver/)
[80] Datasheet of MA-COM MAAPGM0029-Die.
(http://pdf1.alldatasheet.com/datasheet-pdf/view/186258/MACOM/MAAPGM0029-DIE.html)
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