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研究生:林依欣
研究生(外文):Yi-Xin Lin
論文名稱:鈮酸鋰薄膜光電元件之製程開發與研究
論文名稱(外文):Study and fabrication of thin-film lithium niobate photonic devices
指導教授:陳彥宏陳彥宏引用關係
指導教授(外文):Yen-Hung Chen
學位類別:碩士
校院名稱:國立中央大學
系所名稱:光電科學與工程學系
學門:工程學門
學類:電資工程學類
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:118
中文關鍵詞:鈮酸鋰薄膜鈮酸鋰絕熱耦合器定向耦合器脊型波導量子系統
外文關鍵詞:LNOILithium niobateAdiabatic couplerDirectional couplerRidge waveguideQuantum system-on-chip
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本實驗主要開發鈮酸鋰薄膜波導之不同製備方法,並分析及比較各方法之優缺點。本實驗將x-cut鈮酸鋰薄膜波導設計於單模條件下,並透過軟體R-soft之光束傳播法(Beam propagation method, BPM)模擬直波導、絕熱耦合器(Adiabatic coupler, AC)及晶片上的量子系統(Quantum system-on-chip, QSoC)之模態及光傳播情況。
模擬結果顯示,於絕熱耦合器(Adiabatic coupler)有效耦合長度為0.4mm,相比於傳統鈮酸鋰20mm-50mm之耦合長度大幅減小了98%; 並且於晶片尺寸5mm1mm0.5mm之QSoC得到25%:25%:25%:25%之分光比。
波導製備方法分為兩部分,共五種方法,第一部份(方法一、二、四)利用黃光微影、濕蝕刻及乾蝕刻技術於鈮酸鋰薄膜上蝕刻出脊型波導;第二部份(方法三)利用雙束聚焦離子系統(Dual beam-focused ion beam system, FIB),於鈮酸鋰薄膜上蝕刻出線寬0.8m,側壁角度82之脊型波導,並量測TE偏振光總插入損耗~15.77dB,耦合損耗估計為14.19dB,傳播損耗估計為0.35dB/mm;TM偏振光總插入損耗為20.58dB,傳播損耗估計為25.75dB/mm。
另一方面,在與耶拿大學合作下,利用IBEE(Ion-beam enhanced etching)聚焦離子數蝕刻法(方法五),成功量測到AC及QSoC模態分佈,其AC結構總損耗為22.19dB。
在未來工作上,由於此脊狀波導結構於鈮酸鋰薄膜上完成,有別於傳統的鈮酸鋰調制器,可將元件尺度縮小至微米等級,未來配合CMOS等級之電光驅動電壓,可以與矽光子學等相關技術進一步整合,作為重要的矽光子學中之主動調制元件並實現積體化元件。
In order to achieve the waveguiding on the thin-film lithium niobate (TFLN
) substrate, we developed five fabrication methods to compare the advantages and disadvantages in different aspects of these methods.
Our devices are designed under single-mode conditions of 1550-nm band, and we simulated the single mode conditions, the adiabatic couplers (AC) and the quantum system-on-chip (QSoC) structures based on thin-film lithium niobate (TFLN) substrates by using the Beam Propagation Method (BPM) in commercial software of R-soft packages.
We found the effective coupling length of adiabatic couplers (AC) is only 0.4 mm, which is very effective in comparison with standard lithium niobate (LN) ACs with 20-50 mm length, the TFLN-AC coupling length is greatly shortened by 98% in comparison with our previous studies of classical LN ACs. In addition, The QSoC structure size is only 5 mm x 1 mm x 0.5 mm with 25%:25%:25%:25% simulated output splitting ratio, which is also 50 times miniaturization in comparison with the reference of QSoC based on classical LN with 50 mm x 5 mm x 0.5 mm size.
Our devices are designed and fabricated on 0.5-mm-thick x-cut thin-film lithium niobate-on-insulator (LNOI) substrates with thin-film lithium niobate layer of 600 nm above an insulator layer a4700-nm-thick silicon dioxide, and we used five methods to form the ridge waveguides on the surface of TFLN, the etching method is divided into two sections. The first three method (Method 1, Method 2 and Method 4) is wet and dry etching with using photolithography, wet etching and dry etching techniques before the TFLN etching process, these ridge waveguides are etched by inductively coupled plasma-reactive ion etching (ICP-RIE) equipment. For the ICP-RIE etched waveguides, we didn’t observe the stable guiding modes from Method 1 and Method 2, it may due to the high coupling loss and possible the high propagation losses, which may from the uneven channel and rugged surfaces of etched ridge region. The method of the second type (Method 4) is dual beam-focused ion beam system (FIB) etching method. We successfully etched TFLN ridge waveguides with a linewidth of 800 nm and a sidewall angle of 82 degrees by FIB-etching. For chip #FIB9-B, the measured insertion loss is around 15.77 dB of TE-polarized modes, the calculated propagation loss is only 0.35 dB/mm of TE polarization state, and the measured insertion loss ~20.58 dB of TM-polarized modes, the calculated propagation loss is 25.75 dB/mm at TM polarization state.
On the other hand, under the Jena University cooperation project, we used the ion-beam enhanced etching (IBEE) method (Method 5) to etch the TFLN substrates. We successfully measured adiabatic coupler with ~ 22.19 dB insertion loss of TE-polarized modes within the broadband spectral coupling characteristics, and also successfully observed the QSoC mode fields with the power ratio of 10.1%, 32.4%, 50.7% ,and 6.8% for 4 outputs, respectively, which represents and proves the S-bend, Y-branch and directional couplers of QSoC configuration are all have functions.
In the term of future outlook, due to various excellent characteristics of TFLN, the TFLN devices size can be reduced to the hundreds of microns, instead of mm to cm level of classical lithium niobate devices, and according the mode size and excellent electro-optical properties of TFLN, we may imagine in the near future, though the CMOS-compatible electro-optic switching voltages and the standard semiconductor foundries comparable mass-production processes, the TFLN electro-optic modulator (TFLN-EOM) can be further fully integrated with silicon photonics of more variety related technologies, such as integrated photon-detector (PD), integrated laser diode (LD) or even more complex optical circuits, the TFLN EOM can play as key role of important active modulation components in silicon photonics and realize the fully integrated electro-optical circuits (IEOC) in the decade.
目錄
中文摘要 I
ABSTRACT II
致謝 V
目錄 VII
圖目錄 X
表目錄 XIV
第一章 緒論 1
1.1積體光學發展與簡史 1
1.2定向耦合器 (DIRECTIONAL COUPLER) 1
1.3絕熱耦合器 (ADIABATIC COUPLER) 2
1.4 光波導材料 3
1.4.1 絕緣基底矽 (Silicon on isolator) 3
1.4.2 非線性晶體-鈮酸鋰晶體 (LiNbO3, LN) 4
1.4.3 單晶鈮酸鋰薄膜 (Lithium niobate on insulator, LNOI) 6
1.5文獻回顧 7
1.6研究動機 8
1.7內容概要 10
第二章 實驗原理 11
2.1波導簡介 11
2.3拉比共振(RABI OSCILLATION) 17
2.4受激拉曼絕熱(STIMULATED RAMAN ADIABATIC PASSAGE, STIRAP) 19
2.5三斜波導耦合方程式(THREE WAVEGUIDE COUPLER) 20
第三章 晶片設計及模擬結果 24
3.1 LNOI材料基板構造 24
3.2 波導元件設計及模擬結果 25
3.2.1模態定義 25
3.2.2絕熱耦合器(Adiabatic couple, AC) 28
3.2.3晶片上的量子系統(Quantum system-on-chip, QSoC) 33
第四章 晶片製程方法 40
4.1濕蝕刻原理 (WET ETCHING) 40
4.2乾蝕刻原理 (DRY ETCHING) 41
4.3波導製備方法 43
4.4黃光微影及乾蝕刻製程 45
4.4.1 Method 1 :晶片製程步驟 45
4.4.2 Method 1 :Cr遮罩濕蝕刻製程 48
4.4.3 Method 2: Cr遮罩乾蝕刻製程 55
4.4.4晶片清洗方法 58
4.4.5晶片加工 61
4.6場發射雙束型聚焦離子束顯微鏡 (DUAL BEAM FOCUS ION BEAM, FIB) 63
4.6.1聚焦離子束原理 63
4.6.2 聚焦離子束特性限制 64
4.6.3 Method 3:聚焦離子束波導製備方法 65
4.6.4 聚焦離子束蝕刻參數及結果 68
4.7 製程分析及改善 71
4.7.1 ICP-RIE製程改善 72
4.7.2 FIB製程改善 73
4.8 離子束增強型蝕刻(ION BEAM ENHANCED ETCHING, IBEE) 74
第五章 實驗結果與分析 76
5.1導實驗量測架構 76
5.2.1 LNOI黃光微影乾蝕刻波導架構 76
5.2.2 LNOI FIB離子束蝕刻波導架構 77
5.3實驗量測結果與分析 78
5.3.1 LNOI黃光微影乾蝕刻波導量測結果 78
5.3.2 LNOI FIB離子束蝕刻波導量測結果 80
5.3.3 德國耶拿大學IBEE(Ion beam enhanced etching)蝕刻波導 85
5.3.4 脊狀波導保護層模擬分析 89
第六章 結論 91
6.1結論 91
6.2未來展望 92
第七章 參考文獻 94
附錄一 98
本實驗所使用機台 98
圖目錄
圖1- 1 三波導絕熱耦合器[4]。 2
圖1- 2 LNOI基板之電光調制器[24]。 7
圖1- 3 (A)TTD波導於1.55ΜM TE偏振下折射率隨鈦擴散深度分佈圖[26](B) LNOI脊型波導於1.55ΜM TE偏振下下折射率分佈圖。 8
圖1- 4 (A)單個量子晶片結構(5050.5〖MM〗^3) (B)整個量子晶片結構(C)晶片大小比較。[27] 9

圖2- 1光於光波導全反射傳播。 11
圖2- 2定向耦合器耦合區結構示意圖 12
圖2- 3 二能階系統。 17
圖2- 4 三能階系統。 18
圖2- 5三斜坡導結構。 21

圖3- 1 NANOLN,X-CUT LNOI( LITHIUM NIOBATE ON INSULATOR)材料 24
圖3- 2 LNOI晶圓製程: (A) 鈮酸鋰晶體之離子佈植(B) 沉積SIO2於另一塊鈮酸鋰基板上 ; (C)晶體鍵合及分割 (D)退火及化學機械拋光(CMP)。 24
圖3- 3(A) LNOI晶圓結構示意圖 (B) LNOI晶圓之折射率分佈圖。 25
圖3- 4 脊型波導示意圖。 26
圖3- 5 單模、多模模態圖(波導參數:W:1.2M, D:0.6M, LENGTH: 1000M)(A) TE (B) TM。 27
圖3- 6 TE單模模態分佈區域,包含單模、多模、截止區域(黑色區域)。 27
圖3- 7 TM單模模態分佈區域,包含單模、多模、截止區域(黑色區域)。 28
圖3- 8 三斜波導示意圖 29
圖3- 9不同間距下AC光場分佈(LE=400M)。 30
圖3- 10不同間距下AC光場分佈(LE=500M)。 30
圖3- 11不同間距下AC光場分佈(LE=1000M)。 31
圖3- 12 不同間距下AC光場分佈(LE=2000)。 32
圖3- 13 (A) QSOC示意圖(510.5MM3) (B)量子糾纏光子晶片示意圖(晶片尺寸5050.5MM3)[27]。 33
圖3- 14 (A) Y-JUNCTION (B) DIRECTIONAL COUPLER (C) DIRECTIONAL COUPLER 34
圖3- 15 (A)S-BEND 波導示意圖。 34
圖3- 16 S-BEND不同分之長度(LS)光場分佈。 35
圖3- 17 DC波導光場分佈 (A) LOFFSET= 10M (B) LOFFSET= 20M。 36
圖3- 18 QSOC結構示意圖。 37
圖3- 19 QSOC結構部分模擬圖。 37
圖3- 20模擬結果 38
圖3- 21 (A)光源由WGA入射 (B)光源由WGC入射。 39

圖4- 1 LNOI晶片之波導製程歷程圖。 40
圖4- 2 (A)等向性蝕刻(B)非等向性蝕刻。 41
圖4- 3 METHOD 1 :黃光微影流程示意圖 (A)LNOI基板(沉積鉻) (B)塗佈HMDS (C)塗佈PFI38光阻 47
圖4- 4 I-LINE STEPPER。 48
圖4- 5蝕刻流程。 48
圖4- 6 METHOD 1 :CHIP A 量測結果。 52
圖4- 7 METHOD 1: CHIP Z 量測結果。 52
圖4- 8 METHOD 1: CHIP X 量測結果。 53
圖4- 9 METHOD 1: CHIP A、CHIP Z之SEM影像。 53
圖4- 10 METHOD 1: CHIP X 晶之SEM影像。 54
圖4- 11 METHOD 1: CHIP 1.0、CHIP 2.0、CHIP 3.0、CHIP 4.0之SEM影像 。 54
圖4- 12 METHOD 1: CHIP 5.0、CHIP 6.0、CHIP 7.0之SEM影像 (WIDTH: 5M , DEPTH: 240NM)。 54
圖4- 13 METHOD 2: CHIP C波導掀離。 55
圖4- 14 METHOD 2:波導於CR濕蝕刻後SEM影像(A)線寬不平整 (B)底切現象(UNDERCUT)。 55
圖4- 15 METHOD 2: CR 乾蝕刻流程圖。 56
圖4- 16 文獻[59]清洗結果。 58
圖4- 17 METHOD 2: CHIP11晶片清洗情況顯微鏡影像。 59
圖4- 18 METHOD 2: CHIP A 清洗前後之顯微鏡影像 (A)清洗前 (B)ACE清洗後 (C)晶片表面。 59
圖4- 19晶片清洗情況顯微鏡影像。 60
圖4- 20 METHOD 2: CHIP D、CHIP E、CHIP F晶片清洗情況SEM影像。 60
圖4- 21 SF6蝕刻LINBO3表面SEM影像。 61
圖4- 22 METHOD 2: CHIP G、CHIP H晶片清洗情況SEM影像。 61
圖4- 23上臘。 62
圖4- 24細磨完成端面。 62
圖4- 25拋光。 62
圖4- 26 (A)卸臘前晶片端面拋光情況 (B)卸臘完成端面拋光情況。 63
圖4- 27 (A)雙束型聚焦離子束顯微鏡示意圖 (B)鎵離子束撞擊材料表面示意圖。 64
圖4- 28 (A)蝕刻面側壁傾斜(B)窗簾結構。 65
圖4- 29 (A)離子束偏移造成蝕刻位置誤差 (B) 兩段波導銜接點SEM影像。 65
圖4- 30 切薄後晶片SEM影像。 66
圖4- 31 METHOD 3: FIB蝕刻流程圖,紅色方框為蝕刻區域。 68
圖4- 32 METHOD 3: FIB蝕刻完成圖。 68
圖4- 33 METHOD 3:不同機台波導側壁蝕刻結果比較。 69
圖4- 34 METHOD 3:不同機台波導側壁蝕刻結果比較。 69
圖4- 35 METHOD 3: FIB8-E 波導SEM影像。(台灣科技大學) 70
圖4- 36 METHOD 3: FIB8 波導SEM影像。(台灣科技大學) 70
圖4- 37 METHOD 3: FIB10 波導SEM影像。(中央大學) 71
圖4- 38 BOSCH製程[62]。 72
圖4- 39 BOSCH製程SEM影像。 73
圖4- 40 端面沉積PT保護層。 73
圖4- 41 METHOD 5: IBEE波導製程[64]。 74
圖4- 42 METHOD 5: IBEE波導SEM影像圖。 74

圖5- 1波導量測架構示意圖(於中央大學科學二館量測)。 76
圖5- 2 LENSED FIBER,SPOT SIZE: 1.7M。 77
圖5- 3 波導量測架構圖(於台灣半導體研究中心量測)。 77
圖5- 4 (A)光纖與晶片耦合示意圖 (B)光纖與晶片耦合實際圖(高數值孔徑單模光纖,UHNA7)。 78
圖5- 5 (A)、(B)、(C)為METHOD 1: CHIP A在CCD(CHARGE COUPLED DEVICE)下影像(D)、(E)、(F)METHOD 1: CHIP X在CCD(CHARGE COUPLED DEVICE)下影像(於中央大學科學二館量測)。 79
圖5- 6 (A)、(B)、(C)、(D)為光束分析儀(BEAM PROFILER)之光場分佈(於台灣半導體研究中心量測)。 79
圖5- 7 METHOD 1: CHIP A SEM 影像。 80
圖5- 8 (A) METHOD 3: FIB2-B之SEM圖,線寬為0.8M (B) METHOD 3: FIB2-D之SEM圖,線寬為1.8M。 80
圖5- 9 METHOD3: FIB2-B (A)入射波長632NM模態(TE) (B)入射波長1550NM模態(TE) (C)入射波長1580NM模態(TE) (於台灣半導體研究中心量測)。 81
圖5- 10 METHOD3: FIB2-BD(A)入射波長632NM模態(TE) (B)入射波長1550NM模態(TE) (C)入射波長1560NM模態(TE) (D)入射波長1550NM,光纖傾斜入射之模態(TE) (E)入射波長1560NM,光纖傾斜入射之模態(TE) (於台灣半導體研究中心量測)。 81
圖5- 11 METHOD3: FIB2-D波導模態分佈模擬。 81
圖5- 12波導模態定義[66]。 82
圖5- 13 (A)光纖與晶片耦合示意圖 (B)光纖與晶片耦合實際圖(TAPER LENSED FIBER)。 83
圖5- 14 METHOD3: FIB8 模態分佈。 83
圖5- 15 METHOD3: FIB9、FIB10 模態分佈 84
圖5- 16 ADIABATIC COUPLER結構。 85
圖5- 17 METHOD 5:ADIABATIC COUPLER #1,Λ: 1534.8NM-1555.216NM模態分佈(LE:400M,W:1.5M,G:1.8M,G:2.0M)。 85
圖5- 18 METHOD 5: ADIABATIC COUPLER #1,Λ: 1535NM-1570NM模態分佈(LE:400M,W:1.5M,G:1.6M,G:2.2M)。 86
圖5- 19 QSOC結構圖。 88
圖5- 20 METHOD 5: QSOC#1模態分佈(W:1M, LDC1 :38M, LDC2 :128M)。 88
圖5- 21 METHOD 5: QSOC#2 模態分佈,Λ=1536.9905 (W:1M, LDC1 :38M, LDC2 :125M)。 89
圖5- 22 保護層模擬比較。(A-1)覆蓋保護層SIO2脊型波導結構示意圖 (B-1)無覆蓋保護層SIO2脊型波導結構示意圖(A-2)覆蓋保護層SIO2脊型波導結構模擬圖 (B-2)無覆蓋保護層SIO2脊型波導結構模擬圖(A-3)覆蓋保護層SIO2脊型波導結構模態圖(Λ: 1550NM,WIDTH: 0.8M) (B-3)無覆蓋保護層SIO2脊型波導結構模態圖(Λ: 1550NM,WIDTH: 0.8M) (A-4)覆蓋保護層SIO2脊型波導結構光場圖(Λ: 1550NM,WIDTH: 0.8M) (B-4)無覆蓋保護層SIO2脊型波導結構光場圖(Λ: 1550NM,WIDTH: 0.8M)。 90
圖5- 23 (A)二維反向錐形波導 (B)三維錐形波導[67]。 93
圖5- 24光柵耦合[68][69]。 93

表目錄

表1- 1 SOI、LN以及LNOI優缺點比較 6

表3- 1 AC基本參數設置 29
表3- 2 LE=400M (A)耦合效率達80%以上分佈(B)耦合效率。 30
表3- 3 LE=500M (A)耦合效率達80%以上分佈(B)耦合效率。 31
表3- 4 LE=1000M (A)耦合效率達80%以上分佈(B)耦合效率。 32
表3- 5 LE=2000M (A)耦合效率達80%以上分佈(B)耦合效率。 32
表3- 6 QSOC參數設置 38
表3- 7 P1、P2、P3、P4出口於不同耦合長度下分光比。 39
表3- 8 不同入射位置光分光比。 39

表4- 1製程流程細節。 45
表4- 2 蝕刻參數相互關係。 50
表4- 3 METHOD 1 :蝕刻參數。 51
表4- 4 METHOD 2:蝕刻參數。 56
表4- 5 METHOD 2: 各測試晶片之蝕刻參數。 57
表4- 6 METHOD 2:CR與LN之蝕刻參數。 57
表4- 7 METHOD 2: CHIP1,11,12,13,14,15之蝕刻參數。 57
表4- 8 RIE蝕刻及FIB蝕刻優缺點。 71

表5- 1高數值孔徑單模光纖規格(UHNA7)。 82
表5- 2波導模態大小數值。 82
表5- 3 不同工作距離下METHOD3: FIB9-B光損耗分析圖。 84
表5- 4 METHOD 5: P1、P2、P3、P4之分光比。 89

表6- 1 本實驗與其他論文損耗比較表。 92
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