隨著無線通訊技術的發展，5G已經開始蓬勃發展，而資料的傳輸速度與資料量也越來越重要。在本篇論文中，將提出一高傳輸速度與資料量的收發機模組，並說明如何透過設計通道編解碼的方式，來達到更高傳輸速率與高可靠度的品質。
此收發機模組主要透過通道編解碼器以及OFMD調變器，來完成雛型系統的一對一通訊測試。選擇參考在LTE架構下的OFDM調變系統以及DVB-T架構下的通道編解碼規格，來作為實現的模組，並加以修改與擴充，來達到高速率的傳輸速度與演算法

With the development of wireless communication technology, 5G has begun to flourish, and the speed of data transmission and the amount of data are becoming more and more important. In this paper, a transceiver module with high transmission speed and throughput will be proposed, and how to design a channel codec to achieve higher transmission data rate and high reliability.
The transceiver module mainly performs one-to-one communication test of the prototype system through the channel codec and the OFDM modulator. Select the OFDM modulation system under the LTE architecture and the channel codec specification under DVB-T architecture as the implemented module, and modify and expand to achieve high transmission speed and algorithm.

中文摘要 I
ABSTRACT II
謝誌 III
目錄 IV
圖目錄 VI
第一章 緒論 1
1-1 研究動機與背景 1
1-2 章節提要 1
第二章 通道編碼 2
2-1 簡介 2
2-2 通道編碼器 2
2-3 里德所羅門碼編碼器 3
2-4 外部交錯器 5
2-5 摺積碼編碼器 8
2-6 64 QAM BIT-PERMUTATION 8
第三章 通道解碼 9
3-1 簡介 9
3-2 通道解碼器 9
3-3 軟式決策器 10
3-4 64 QAM BIT DE-PERMUTATION 20
3-5 摺積碼解碼器 20
3-6 DETECT PACKET HEADER 21
3-7 外部解交錯器 22
3-8 里德所羅門碼解碼器 23
第四章 模擬與效能比較 24
4-1 簡介 24
4-2 64QAM BIT-PERMUTATION模擬 24
4-3 外部交錯器模擬 25
第五章 硬體架構設計 27
5-1 硬體簡介 27
5-2 通道編碼器硬體架構 27
5-2-1 里德所羅門碼編碼器 28
5-2-2 外部交錯器 29
5-2-3 摺積碼編碼器 32
5-3 通道解碼器硬體架構 33
5-3-1 軟式決策器 33
5-3-2 摺積碼解碼器 35
5-3-3 Detect Packet Header 36
5-2-4 外部解交錯器 39
5-2-5 里德所羅門碼解碼器 42
第六章 軟體定義無線電平台與硬體實驗結果 48
6-1 軟體定義無線電 48
6-2 軟體定義無線電平台 48
6-3 FPGA(AC701) 49
6-4 RF MODULE(AD9361) 50
6-5 硬體使用資源 51
第七章 結論 52
參考文獻 53

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