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研究生:蔡尚諮
研究生(外文):Shang-Tzu Tsai
論文名稱:應用於5G通訊系統之採用電容源退化耦合技術低相位雜訊正交壓控振盪器
論文名稱(外文):Design of A low phase noise Quadrature Voltage Controlled Oscillator using Capacitive Source Degeneration Coupling technology for 5G systems
指導教授:翁若敏
指導教授(外文):Ro-Min Weng
口試委員:邱煥凱黃崇禧林宗賢
口試委員(外文):Hwann-Kaeo ChiouChorng-Sii HwangTsung-Hsien Lin
口試日期:2020-06-19
學位類別:碩士
校院名稱:國立東華大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:66
中文關鍵詞:基底偏壓技術雙耦合低電壓正交壓控振盪器電容源退化耦合技術
外文關鍵詞:body-bias technologydual couplinglow voltagequadrature voltage-controlled oscillatorcapacitive source degeneration coupling technology
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在二十一世紀無線通訊產品迅速發展,在無線通訊物聯網及手機資料傳輸量越來越大下,高速低延遲的無線系統產品進而產生。在無線系統裡的低功耗、低相位雜訊成為等目標,而無線通訊前端收發機的射頻電路系統中,不可或缺的壓控振盪器(Voltage-controlled Oscillator ; VCO)成為提供純淨以及穩定的重要電路。電路使用台灣積體電路製造公司(Taiwan Semiconductor Manufacturing Company ; tsmc) 0.18 µm 1P6M CMOS 製程模擬與實作。

本論文中所設計的第一顆電路為操作於超低電壓下之正交壓控振盪器採用基底偏壓技術。操作頻率在17.35~18.52GHz。使用基底偏壓技術來使操作電壓下降至0.4V。核心消耗功率為7.28mW。在載波頻率1MHz處的相位雜訊為-100.973dBc/Hz。相位誤差最大值為4.408度。

本論文中所設計的第二顆電路為操作於24-25GHz頻段之低相位雜訊正交壓控振盪器採用電容源退化耦合技術應用於5G通訊系統。操作頻率在24~25.28GHz。核心消耗功率為20.04mW。電路架構中增加了電容源退化耦合電容,讓整體電路能有更好的相位雜訊。在載波頻率1MHz處的相位雜訊-103.536dBc/Hz。相位誤差最大值為4.632度。
In the 21st century, wireless communication products have developed rapidly. With the increasing volume of wireless communication Internet of Things and mobile phone data transmission, high-speed and low-latency wireless system products have emerged. Low power and low phase noise in wireless systems have become the target, and in the radio frequency circuit system of wireless communication front-end transceivers, the indispensable voltage controlled oscillator (VCO) has become an important circuit that provides purity and stability. The presented VCOs are designed and fabricated by using tsmc 0.18m CMOS 1P6M process.

The circuit of the chapter 3 was proposed using a substrate bias technique for a quadrature voltage controlled oscillator at ultra-low voltage. The circuit was operated in 17.35-18.52 GHz. The substrate bias technique is used to reduce supply voltage. Therefore, this QVCO chip was operating at 0.4V. The core power consumption is 7.28mW. The phase noise was -99.7dBc/Hz at the carrier frequency of 1MHz. The maximum phase error was 4.408 degrees.

The circuit of the chapter 4 was proposed using a low phase noise quadrature voltage controlled oscillator using capacitive source degeneration coupling technology for 5G systems. The circuit was operated in 24-25 GHz. The core power consumption is 20.04mW.The phase noise was -103.536dBc/Hz at the carrier frequency of 1MHz. The maximum phase error was 4.632 degrees.
第一章 序論 1
1.1 研究背景與動機 1
1.2 K頻段系統簡介 2
1.3 5G通訊系統頻段簡介 3
1.4 論文架構介紹 4
第二章 壓控振盪器介紹及原理分析 5
2.1 壓控振盪器介紹 5
2.2 壓控振盪器之原理介紹 5
2.2.1 振盪器分析 5
2.2.2 電容電感振盪器(LC-Tank Oscillator)基本架構 6
2.2.3 傳統(LC-Tank VCO)介紹 8
2.2.4 傳統正交(LC-Tank Oscillator)介紹 9
2.3 壓控振盪器重要參數介紹 11
2.4 相位雜訊(Phase Noise) 12
2.4.1 相位雜訊-熱雜訊(Thermal Noise) 13
2.4.2 相位雜訊-閃爍雜訊(Flicker Noise) 15
2.4.3 相位雜訊-散彈雜訊 20
2.5 文獻回顧 21
2.5.1 206-220 GHz CMOS 壓控振盪器使用基底偏壓技術 21
2.5.2 具有電容源極退化耦合與自發跨導匹配技術的QVCO系統分析 22
2.6 設計流程 23
第三章 超低電壓下正交壓控振盪器採用基底偏壓技術 25
3.1 超低電壓下之正交壓控振盪器採用基底偏壓技術介紹 25
3.1.1 電路架構與設計 25
3.1.2 雙耦合(Dual Coupling) 26
3.1.3 基底偏壓技術(body-bias) 29
3.1.4 元件選擇 29
3.1.5 緩衝電路(Buffer Circuit) 30
3.2 模擬結果與量測結果 31
3.2.1 模擬結果(Simulation Results) 31
3.2.2 電路佈局(Circuit layout) 38
3.2.3 量測結果(Measurement Results) 39
3.2.4 比較與結果討論 46
第四章 應用於5G通訊系統之採用電容源退化耦合技術低相位雜訊正交壓控振盪器 47
4.1 應用於5G通訊系統之採用電容源退化耦合技術低相位雜訊正交壓控振盪器 47
4.1.1 電路架構與設計 47
4.1.2 電容源退化耦合(Capacitive Source Degeneration Coupling) 48
4.2 模擬結果與量測結果 53
4.2.1 模擬結果(Simulation Results) 53
4.2.2 電路佈局(Circuit layout) 60
4.2.3 量測結果(Measurement Results) 61
4.2.4 比較與結果討論 63
第五章 結論與未來展望 65
5.1 結論 65
5.2 未來展望 65
[1]B. Razavi, “RF Microelectronics,” Prentice-Hall, 1997.
[2]Qualcomm, “Spectrum for 4G and 5G,” https://www.qualcomm.com/media/documents/files/spectrum-for-4g-and-5g.pdf
[3]YourStory, “MWC Americas:EVP Cristiano Amon discusses Gigabit LTE and 5G in the digital economy,”
https://yourstory.com/2017/09/mwc-americas-cristiano-amon-discusses-gigabit-lte-5g?utm_pageloadtype=scroll
[4]B. Razavi, “Design of Analog CMOS Integrated Circuits,” The McGraw-Hall
Companies, Inc., Chap. 15, 2001.
[5]江堯昌,20/40GHz雙頻帶雙推式壓控振盪器與20GHz雙正交耦合四相位壓控振盪器之設計,國立東華大學電機工程研究所碩士論文,民國一百零三年
[6]李侑娟,使用雙偶合回授或被動混合B/C類技術之低相位雜訊壓控振盪器,國立東華大學電機工程研究所碩士論文,民國一百零六年
[7]T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 2004.
[8]Rael, J.J. and A.A. Abidi. “Physical processes of phase noise in differential LC oscillators,” in Custom Integrated Circuits Conference, Proceedings of the IEEE, 2000.
[9]Hajimiri, A. and T.H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp. 179-194, 1998.
[10]Po-Han Chiang, Jen-Hao Cheng, Yi-Ching Wu, et al, “A 206 ∼ 220 GHz CMOS VCO using body-bias technique for frequency tuning,” 2015 IEEE MTT-S International Microwave Symposium,27 july, 2015.
[11]Qian Zhou, Shifeng Zhang, Lu Jie, et al, “A 40 nm CMOS V-band VCO with on-chip body bias voltage control technique,” International Conference on Communication Control and Intelligent Systems (CCIS),Nov, 2016.
[12]Shuenn-Yuh Lee, Chun-Jung Chiu, and Hao-Yun Lee, “Systematic Analysis of Quadrature VCO With Capacitive Source Degeneration Coupling and Spontaneous Transconductance Matching Techniques,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 66, no. 4, pp. 517-521, April, 2019.
[13]C. Hong, C. Wu and Y. Liao,” Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 1, pp. 16-20, Jan, 2015.
[14]陳婉茹,應用於無線通訊系統之低成本高性能接收機前端電路設計,國立東華大學電機工程研究所碩士論文,民國一百零八年
[15]S. Saberi and J. Paramesh, “A 11.5–22GHz dual-resonance transformer-coupled quadrature VCO,” 2011 IEEE Radio Frequency Integrated Circuits Symposium, Baltimore,July, 2011.
[16]H. Chang and Y. Chiu, "K-Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications," in IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 1, pp. 46-59, Jan, 2012.
[17]H. Chang, C. Lin, Y. Liu, Y. Yeh, K. Chen and S. Wu, "65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator," in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 6, pp. 2402-2413, June, 2013,
[18]M. Li, Y. Liao and H. Chang, "A K-band low power high accuracy quadrature VCO using gate-modulated coupling and transformer feedback technique," 2014 Asia-Pacific Microwave Conference, Sendai, Japan, 2014.
[19]N. Kuo, J. Chien and A. M. Niknejad, "Design and Analysis on Bidirectionally and Passively Coupled QVCO With Nonlinear Coupler," in IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 4, pp. 1130-1141, April, 2015.
[20]T. He, R. Zhang, H. Yang, J. Wang and C. Shi, "A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018.
[21]H. Yang, I. Y. Shen and H. Chang, "A K-band CMOS Low-Phase-Noise Sub-harmonically Injection-Locked QVCO with Divider-less Frequency-tracking Loop," 2019 IEEE MTT-S International Microwave Symposium (IMS), May, 2019.
[22]R. Weng, R. Huang and Y. Chiang, "K-band low-power dual-hybrid-coupling quadrature voltage-controlled oscillator," in IET Microwaves, Antennas & Propagation, vol. 14, no. 1, pp. 75-81, Jan, 2020.
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