本論文旨在設計製作低雜訊、高增益之低雜訊放大器，並利用低雜訊放大器進行微波輻射計系統的組合與量測，以應用於量測人體皮下溫度。吾人透過低雜訊放大器的特性作為微波輻射計系統前端放大電路，以降低雜訊對微波輻射計系統之量測影響，並冀望較高之增益使微弱熱輻射訊號放大至足夠提供功率檢測器進行轉換，本文使用兩種不同製程之電路實現低雜訊放大器，並進行微波輻射計系統的架設與量測。製作本文之低雜訊放大器時，吾人選用CMOS製程與HEMT製程之離散元件電晶體，CMOS製程擁有低功耗、面積小的特性，而HEMT製程則擁有低雜訊指數、高轉導的特性，兩種製程各有其優點，電路設計操作於較不受其他頻段干擾之GPS頻段1.575 GHz，在最後以全功率輻射計架構進行微波輻射計系統製作與量測。
積體電路形式之低雜訊放大器採用台積電TSMC 0.18 µm RF CMOS製程，微波頻段之放大器電路透過疊接的方式預防出現寄生電容所會產生的米勒效應，並串接二級電路完成低雜訊放大器，以達到在單顆晶片上高增益、低雜訊指數、小面積與低功耗這些目標。晶片於台灣半導體研究中心進行量測，於VDD使用0.6 V、VB使用0.7 V時，量測得的S11為-14.7 dB，S22為-12.96 dB，S21為15.40 dB，雜訊指數為3.27 dB，IIP3計算約為-3.5 dBm，功率消耗約為1.98 mW，研究發現當電源電壓高至1 V時晶片產生振盪。
離散式元件採用的是Avago公司的ATF-55143電晶體，以及Murata公司所生產的晶片電阻、電容與電感，以印刷電路板方式實現混成式低雜訊放大器製作，電路採用的是單級共源級架構，並使用L型匹配電路搭配電感退化性放大器架構實現設計，電路使用ADS模擬軟體進行模擬設計，實作電路經匹配後測得S11與S22為-5.3 dB、-20 dB，S12為-19.2 dB，S21為10.2 dB，雜訊指數約為1.2 dB。
由於設計之ATF-55143混成式低雜訊放大器性能不佳，改使用ATF-54143製作之低雜訊放大器進行全功率輻射計之架設與量測。由兩個低雜訊放大器、一個帶通濾波器形成前端電路，再輸出至功率檢測器轉換直流電壓。全功率輻射計使用射頻訊號產生器直接輸入進行量測，輸入由-65 dBm開始至-15 dBm，量測發現全功率輻射計系統可以順利的將射頻訊號轉換直流電壓，其系統轉換射頻訊號與直流電壓成對數關係，且在輸入訊號大於-50 dBm時，系統輸出的直流電壓有明顯成長。使用低雜訊放大器做為微波輻射計之放大級，如能將接收的人體熱輻射訊號放大至足夠功率檢測器轉換，即可以透過微波輻射計系統對溫度進行分析，研究發現若低雜訊放大器設計良好之情況下其效能可以符合微波輻射計系統之需求。

The paper aims to design a low noise amplifier (LNA) to achieve low noise but high gain. The LNA is configured at the RF front-end of the microwave radiometer system that is employed to measure the temperature of human subcutaneous. The LNA circuit of the microwave radiometer system can help to reduce the influence from added noise. The high gain of the LNA is capable of amplifying the signal so that it is easy to launch the signal into the power detector to convert to DC voltage. The paper uses CMOS process and HEMT process to fabricate the LNAs. The features of CMOS are low power consumption and small chip area, but those of the HEMT process are low noise and high transconductance. The circuit was designed in the GPS Band, 1.575 GHz. The fabricated microwave radiometer system is one kinds of a total-power radiometer architecture.
The first type LNA is implanted by using TSMC 0.18 µm RF CMOS process. The modified-cascode topology is applied to the CMOS LNA to reduce the Miller effect. The two stages LNA is made by cascade topology in order to achieve the goals of high gain, low noise figure, small area and low power consumption on a single chip. The chip was measured at the TSRI. When using 0.6 V for VDD, 0.7 V for VB, the measured S11 is -14.7 dB, S22 is -12.96 dB, S21 is 15.4 dB, and noise figure is 3.27 dB. The measured IIP3 is approximately -3.5 dBm, and power consumption is only 1.98 mW. The research found that oscillation will be generated as the power supply voltage increases to 1 V.
Discrete components were assembled to fabricate the second type LNA. An Avago’s ATF-55143 transistor was utilized to design the hybrid low-noise amplifier. The LNA is designed using a common source topology of single-stage amplifier architecture. The design used an L-section method to perform impedance matching and utilized inductive degeneration feedback to reduce instability. The ADS circuit simulator was employed to perform RF circuit simulation and design. The measured S11 and S22 are -5.3 dB, -20 dB respectively, S12 is -19.2 dB, S21 is 10.2 dB, and noise figure is approximately 1.2 dB.
Since the input matching of the hybrid LNA is imperfect, the active part replaced by ATF-54143 was used to set up the total power radiometer. The front-end circuit of the radiometer is composed of two low noise amplifiers and a band-pass filter. The power detector converts the RF signal of the front-end into DC voltage output. The input power level of the RF signal generator starts from -65 dBm to -15 dBm. The RF signal and the converted DC output voltage has a logarithmic relationship, and the DC output has obvious change when the input power increases to -50 dBm. If the thermal radiation signal inside human body is amplified enough, the microwave radiometer system can retrieve the temperature information. The study verified that the performance of the low noise amplifier meets the requirements of the microwave radiometer system.

摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第 1 章 緒論 1
1.1 研究動機 1
1.2 文獻探討 2
1.3 章節介紹 4
第 2 章 低雜訊放大器介紹 6
2.1 雜訊分析 6
2.1.1 熱雜訊 6
2.1.2 散射雜訊 7
2.1.3 閃爍雜訊 7
2.1.4 雜訊指數 7
2.1.5 半導體元件雜訊來源 8
2.2 穩定度 9
2.3 線性度 9
2.3.1 1-dB增益壓縮點(1-dB Compressed Point, P1dB) 10
2.3.2三階交互調變失真(Third Order Intermodulation Distortion) 10
2.4 CMOS與HEMT元件比較 10
2.5常用低雜訊放大器架構 11
2.5.1 電阻匹配式放大器 11
2.5.2 電感退化性放大器 11
2.5.3並串回授式放大器 11
2.5.4 1/gm匹配式放大器 11
2.5.5放大器架構整理比較 12
2.6全功率輻射計介紹 12
2.7功率檢測器介紹 13
第 3 章 T18 CMOS低雜訊放大器設計 21
3.1電路架構與設計 21
3.1.1 疊接架構 21
3.1.2 基體偏壓 22
3.2電路模擬 22
3.3佈局考量 25
3.4量測結果 25
第 4 章 混成式低雜訊放大器與微波輻射計 47
4.1電路架構與設計 47
4.2電路模擬 47
4.3低雜訊放大器量測結果 48
4.4功率檢測器與濾波器 49
4.5微波輻射計系統量測 50
第 5 章 結論與未來展望 70
參考文獻 72

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