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研究生:張靖
研究生(外文):Chang, Ching
論文名稱:鐵電氧化鉿鋯於環繞式閘極電晶體(GAA)及用於疊接氮化鎵高電子遷移率電晶體(HEMT)
論文名稱(外文):Ferroelectric HfZrO2 for GAA-FET and GaN HEMT Cascode Application
指導教授:李敏鴻
學位類別:碩士
校院名稱:國立臺灣師範大學
系所名稱:光電工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:53
中文關鍵詞:鰭式電晶體環繞式閘極電晶體次臨界擺幅
外文關鍵詞:FinFETGAA FETSub-threshold swing
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近年來隨著智慧型手機、物聯網(IoT)的發展,元件都必須具有體積小、高效能等特點,目前可以透過鰭式電晶體、環繞式閘極電晶體等多閘極電晶體,使閘極能夠有效控制元件,降低漏電流,解決元件尺寸持續微縮,所造成的短通道效應,以延續摩爾定律(Moore’s Law);5G通訊、電動車發展之下,功率元件需求大增,由於氮化鎵材料耐高溫高壓,並且具有的極高電子遷移率和寬能隙等特性相當符合功率元件使用。
本論文分為三個部分,第一部分實驗,在矽基板上堆疊二氧化矽和多晶矽用來取代 SOI 晶圓以降低成本,並以鐵電材料Hf1-xZrxO2 (HZO) 作為介電層,其中介電層分為兩種,一種為單層Hf0.5Zr0.5O2 ,另一種以2層Hf0.5Zr0.5O2 夾著Al2O3 ,應用於環繞式閘極電晶體,進行 Endurance和Retention量測。第二部分探討GaN 高電子遷移率電晶體(HEMT)的元件特性。最後一部分將鐵電電晶體與氮化鎵HEMT疊接,利用鐵電材料之負電容效應,改善次臨界擺幅(SS),並且提升臨界電壓,使氮化鎵HEMT變為增強型(E-mode),讓此疊接電路同時具備氮化鎵HEMT和鐵電電晶體之特性。
In recent years, with the development of smartphones and the Internet of Things (IoT), devices must have the characteristics of small size and high performance. The development of multi-gate transistors, such as FinFET and GAAFET, may benefit the well gate control and reduce the short-channel effect with minimizing leakage current for scaling down feature size of the device. With the development of 5G communication and electric vehicles, the demand for power devices has increased greatly. Because the gallium nitride material can withstand high voltage and high temperature, it has extremely high electron mobility and wide energy gap are quite in line with the use of power devices.
This thesis is divided into three parts: Firstly, ferroelectric Hf1-xZrxO2(HZO) as gate insulator integrated with GAAFET is performed. Stacking SiO2 and Poly-Si on the Si substrate to replace SOI wafer has an advantage of cost reduction. The measurement of endurance and retention are carried out for single and double HZO GAAFET. Then, AlGaN/GaN HEMT (high electron mobility transistors) are discussed in the second part. Finally﹐by employing a cascaded structure﹐the D-mode GaN HEMT can be combined with HZO negative capacitance Si-FET to present steep slope and normally-off characteristics.
Publication I
期刊論文 I
研討會論文 I
中文摘要 III
Abstract IV
致謝 V
目錄 VI
圖目錄 IX
表目錄 XI

第一章 緒論 1
1-1 多閘極電晶體簡介 1
1-2 鐵電材料簡介 4

第二章 8
2-1 實驗動機 8
2-2 鐵電環繞式閘極電晶體製程 9
2-2-1晶圓清洗和爐管沉積 9
2-2-2元件通道製程 10
2-2-3乾式蝕刻和Trimming 薄光阻 12
2-2-4熱氧化消耗元件通道 14
2-2-5沉積High-K介電層 14
2-2-6閘極製程 15
2-2-7快速熱退火 16
2-3 鐵電環繞式閘極電晶體分析和電性量測 18
2-3-1結構分析 18
2-3-2 IDS-VGS量測 21
2-2-3 Endurance 量測 24
2-2-3 Retention量測 25
2-4 結果討論 26

第三章 氮化鎵HEMT元件 27
3-1 簡介 27
3-1-1 氮化鎵簡介 27
3-1-2 氮化鎵磊晶簡介 28
3-1-3 氮化鎵材料特性 29
3-2 氮化鎵高電子遷移率電晶體(HEMT)製程 32
3-2-1 試片雷射切割 32
3-2-2 試片表面清潔 32
3-2-3 黃光製程 32
3-2-4 金屬電極製程 33
3-2-5 閘極製程 33
3-3 氮化鎵元件分析和電性量測 35
3-4 結果討論 37

第四章 鐵電電晶體疊接於氮化鎵HEMT 38
4-1 簡介 38
4-1.1 氮化鎵元件臨界電壓簡介 38
4-1.2 鐵電材料之負電容效應簡介 41
4-2 氮化鎵元件疊接電性量測 43
4-3結果討論 47

第五章 48
5-1總結 48
5-2 未來工作 49

參考資料 50
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