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研究生:許乃文
研究生(外文):Nai-Wen Hsu
論文名稱:無摻雜矽/矽鍺異質結構低溫非揮發性記憶體
論文名稱(外文):Cryogenic non-volatile memory devices based on undoped Si/SiGe heterostructures
指導教授:李峻霣
指導教授(外文):Jiun-Yun Li
口試委員:李敏鴻陳敏璋羅廣禮吳肇欣
口試委員(外文):Min-Hung LeeMiin-Jang ChenGuang-Li LuoChao-Hsin Wu
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:61
中文關鍵詞:無摻雜矽/矽鍺異質結構低溫記憶體表面穿隧效應
外文關鍵詞:undoped Si/SiGe heterostructurecryogenic memorysurface tunneling
DOI:10.6342/NTU202000005
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無摻雜矽/矽鍺異質結構(undoped Si/SiGe heterostructures)的量子點元件具有製作大型量子系統的潛能。然而,要利用室溫的古典元件控制低溫的量子元件仍有一些困難需要克服。本論文中,我們以無摻雜矽/矽鍺異質結構製作能於低溫環境下操作且耐久力表現優異的記憶體元件。藉由施加正的閘極偏壓,電子可由底層的矽量子井穿隧到表面,並侷限(trapped)在介面能態(interface states)中。若對元件閘極施加負偏壓,電子則會逃離介面能態。因此,我們可以調變元件的閾值電壓(threshold voltage),使元件作為低溫記憶體操作。
為了深入探討無摻雜矽/矽鍺異質結構中表面穿隧效應的物理機制及其對溫度的變化,我們在4 ~ 300 K下對元件進行電容電壓量測及霍爾量測,以探討元件的電荷分布情形與載子的傳輸特性。我們觀察到元件在低溫環境下(T ≤ 35 K),具有兩階段的導通機制,低電壓時,僅底層的量子井導通,而高電壓時,表面通道與底層量子井同時導通,表現出雙層導通(bilayer conduction)的特性。而當溫度高於50 K時,元件特性則是受雙層導通主導。
我們將無摻雜矽/矽鍺異質結構製作成記憶體元件,並量測了元件在4 ~ 120 K下的記憶體元件特性,包含寫入(program)速度、抹除(erase)速度、電荷保存力(retention)及耐久力。隨著溫度增加,元件的抹除速度加快,電荷保存力變差,而寫入速度及耐久力的表現則沒有明顯的變化。矽/矽鍺異質結構記憶體元件具有優異的耐久力。這是由於電子在寫入的過程中穿隧經過晶格化的矽鍺層,避免了傳統快閃記憶體元件電子需穿隧氧化層導致氧化層崩潰(oxide breakdown)的潛在問題。
Quantum dots on undoped Si/SiGe heterostructures are very promising for large-scale qubit systems. However, to interface the room-temperature classical control devices to cryogenic quantum devices is challenging. In this thesis, a Si/SiGe heterostructure cryogenic flash memory by surface tunneling is demonstrated with high endurance. By applying positive (or negative) gate biases, electrons in the buried Si QW can tunnel to (or out of) the surface and are trapped (or detrapped) in the interface states. The threshold voltage of the device can be modulated and the device works as a cryogenic memory.
To investigate the physics of surface tunneling in undoped Si/SiGe heterostructures and its temperature dependence, capacitance-voltage (C-V) and Hall measurements were performed at 4 ~ 300 K to study the charge distributions and the carrier transport properties of the devices. At low temperatures (T ≤ 35 K), the device shows two stages of conduction. At lower gate voltages, only the buried QW conducts, while at higher gate voltages, parallel conduction of both surface layer and buried QW dominates. For temperatures higher than 50 K, bilayer conduction dominates the device characteristics.
Undoped Si/SiGe heterostructure flash memory devices were fabricated and characterized. The memory device characteristics such as program speed, erase speed, retention, and endurance tests were measured at 4 K to 120 K. As temperature increases, erase becomes faster with the degraded retention while no significant change is observed for the program speed and endurance performance. The devices show excellent endurance since the tunneling occurs in the crystalline SiGe layer, which could avoid the potential oxide breakdown common for conventional flash memory devices.
口試委員會審定書 i
誌謝 ii
摘要 iii
ABSTRACT iv
CONTENTS v
LIST OF FIGURES vii
Chapter 1 Introduction 1
1.1 Semiconductor Quantum Computing 1
1.2 Quantum-Classical interface 3
1.3 Overview of the thesis 6
Chapter 2 Temperature-Dependent C-V Characteristics and Transport Properties of Undoped Si/SiGe Heterostructures 8
2.1 Surface Tunneling in Undoped Si/SiGe Heterostructures 8
2.2 Experiment 14
2.3 C-V Characteristics and Magneto-Transport properties 16
2.4 Summary 26
Chapter 3 Non-Volatile Memory Devices of Undoped Si/SiGe Heterostructures 28
3.1 Introduction to Flash Memory and Cryogenic Memory 28
3.2 Device Characteristics of a Si/SiGe Memory at 4 K 33
3.3 Temperature Dependence of Flash Device Characteristics 41
3.4 Summary 46
Chapter 4 Conclusions and Future Work 47
Bibliography 50
Related Publication List 61
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