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研究生:鄭景鴻
研究生(外文):Ching-Hung Cheng
論文名稱:使用貝氏訊號機率模型的轉態延遲錯誤測試圖樣產生技術
論文名稱(外文):Transition Delay Fault Test Pattern Generation Using a Bayesian-Based Signal Probability Model
指導教授:黃俊郎黃俊郎引用關係
指導教授(外文):Jiun-Lang Huang
口試委員:黃炫倫劉建男
口試委員(外文):Xuan-Lun HuangChien-Nan Liu
口試日期:2020-08-14
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:44
中文關鍵詞:自動圖樣測試產生系統
外文關鍵詞:Automatic Test Pattern Generation
DOI:10.6342/NTU202003938
相關次數:
  • 被引用被引用:0
  • 點閱點閱:200
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  • 收藏至我的研究室書目清單書目收藏:0
現代的高效能積體電路對於操作頻率的需求逐年提升,也因此對於延遲錯誤的偵測需求愈發重視。基於全掃描鍊的轉態延遲錯誤測試是一種廣泛被使用於偵測延遲錯誤的方法。在傳統的測試品質項目中,錯誤涵蓋率與測試圖樣數目是最重要的指標。最近的趨勢則是更進一步要求測試過程中的電力消耗與正常操作模式時相近—過高與過低的電力消耗分別會造成過度測試與測試逃脫的問題。
本論文所提出的轉態延遲錯誤自動化測試圖樣產生器以基於貝氏理論的訊號機率模型取代傳統的COP與SCOAP可測試性指標,藉以提高測試圖樣的錯誤偵測能力並使其功率消耗更接近正常的模式。貝式訊號機率模型因為考慮電路裡常見的重收斂扇出,因此比COP與SCOAP更精確的預測電路行為。在產生測試圖樣的過程中,這可以降低錯誤的決定,因此提高錯誤偵測率。此外,我們亦使用基於貝氏理論的訊號機率模型來設定ATPG未指定的信號值。實驗結果顯示,採用貝氏理論訊號機率模型確實能提高錯誤偵測率並降低測試功率。
With the growing operating frequencies of modern high-performance ICs, delay fault testing becomes mandatory. Currently, transition delay fault is the most popular delay fault mode. In the past, fault coverage and test size are the two most important test quality metrics. Recently, it is further required that test power consumption be similar to the functional mode power consumption — excessive test power consumption has been known to cause overkill; low test power consumption, on the other hand, may cause test escape.
In this thesis, we propose to replace the conventional COP and SCOAP testability measure with Bayesian-based signal probability model. The goal is to improve the test pattern set quality and to produce a more functional-like power consumption behavior. Being re-convergence aware, the Bayesian-based signal probability model can more accurately predict circuit behavior. As a result, it reduces the possibility of conflicting PI/PPI assignments and improves fault detection efficiency. Furthermore, we also utilized the Bayesian model to guide the X-fill process. Experimental results show that the proposed ATPG improves fault coverage and lowers test power consumption.
口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vi
表目錄 viii
第1章. 緒論 1
1.1 研究背景 1
1.1.1 延遲錯誤測試(Delay Fault Testing) 1
1.1.2 重收斂扇出(Re-convergence) 1
1.1.3 電力消耗(Power Consumption) 2
1.2 動機 3
1.3 貢獻 3
1.4 論文架構簡介 3
第2章. 預備知識 5
2.1 貝式網路 5
2.2 貝氏推論 6
第3章. 提出方法 11
3.1 基於貝氏訊號機率模型的轉態延遲故障自動化圖樣產生系統(BN-based TDF ATPG) 11
3.2 訊號機率模型 13
3.2.1 建立訊號機率模型 13
3.2.2 近似訊號機率模型建立 14
3.3 基於貝氏訊號的測試圖樣生成(BN-based TPG) 16
3.3.1 基於功能模式下的訊號機率(Functional Mode Signal Probability) 16
3.3.2 基於事件驅動的動態貝氏網路訊號機率更新(Event-Driven Dynamic Bayesian Network Update, EDB) 20
3.3.3 基於貝氏網路之不理會位元填充方法(BN-Fill) 28
第4章. 實驗結果 29
4.1 實驗環境設定 29
4.2 錯誤涵蓋率與測試圖樣數目結果 29
4.2.1 訊號機率模型差異 29
4.2.2 BN-Based TPG 實驗結果 30
4.2.3 EDB對於錯誤涵蓋率影響 33
4.3 基於貝氏網路之不理會位元填充方法 35
4.3.1 針對開關活動之影響 35
4.3.2 對錯誤涵蓋率以及測試圖樣數目之影響 36
4.4 運行時間 37
4.5 實驗總結以及全部實驗數據 38
第5章. 結論 42
文獻參考 43
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K. Chen, C. Chen and J. Huang, "Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime," in International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2019, pp. 1-2.
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T. Zhang and D. M. Hank Walker, "Power supply noise control in pseudo functional test," in VLSI Test Symposium (VTS), 2013, pp. 1-6.
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Xiaoqing Wen et al., "Low-capture-power test generation for scan-based at-speed testing," in International Conference on Test, 2005, pp. 10.
R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Static compaction techniques to control scan vector power dissipation," in VLSI Test Symposium, 2000, pp. 35-40.
S. Remersaro, X. Lin, Z. Zhang, S. M. Reddy, I. Pomeranz and J. Rajski, "Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs," in International Test Conference, 2006, pp. 1-10
C. Chen, C. Cheng, J. Huang and K. Chakrabarty, "Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model," in European Test Symposium (ETS), 2020, pp. 1-6.
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