臺灣博碩士論文加值系統

本篇論文主要在研究由周圍耦合電極之深空乏現象，而在中心之金屬―絕緣層―半導體穿隧二極體所引發之暫態電流及耦合感應電壓衰減之延遲現象。當周圍耦合金氧半穿隧二極體進入深空乏後，可觀察到由蕭基位障調變效應所造成之電壓衰減速度隨氧化層厚度越薄而越慢之現象。在中心穿隧二極體所上所引發之暫態電流為為供給周圍耦合電極其所欠缺之少數載子而產生，而在中心穿隧二極體所上所引發之耦合電壓則為受到周圍深空乏之擾動所感應產生。暫態電流之延遲行為能以從周圍耦合電極洩漏之電洞受到蕭基位障調變解釋。另一方面，耦合感應電壓衰減之延遲現象則是由於新產生之少數載子均受到橫向電場影響而漂移至周圍耦合電極所導致。隨著氧化層厚度的增厚、耦合電極間隙的減少及增加電洞的抓陷，兩金氧半穿隧二極體之間的耦合程度可受到增強，進而導致暫態電流及耦合感應電壓的提升。由於在中心之金氧半穿隧二極體所引發之耦合感應電壓之留存時間並不隨上述因素之影響而有大幅衰弱之情形，其有潛力成為新型記憶體之記憶體特徵。本篇論文中提出一新型耦合金氧半記憶體之架構，並示範該記憶體之實際操作。該記憶體元件唯有當氧化層厚度薄於26 Å後其記憶體特徵才會出現所希望利用之延遲行為，並且此記憶體展現出良好的留存時間(約為5.3秒)及非常低之操作功耗(約為36.16皮瓦特)。

In this thesis, the prolonged transient current and the coupled voltage retention behavior of ultra-thin oxide MISTD induced by deep depletion of surrounded coupling electrode is investigated. Once the Ring MISTD is under deep depletion, the voltage decay speed reduces with decreasing oxide thickness, which is a result of the Schottky barrier modulation effect. The transient current is induced to supply minority carriers to the surrounded coupling electrode while the coupling voltage sensed is the result of the perturbation by the nearby deep depletion. The prolonged transient behavior of the sensed current is explained by the modulation of the hole leakage from the Ring MIS. Also, the prolonged behavior of the coupled voltage retention is the result of the generated electrons being swept towards the Ring MIS by lateral field. By increasing oxide thickness, reducing coupling gap width and increasing trapping holes, the coupling between the two MISTDs are enhanced and thereby increase the sensed current or voltage. Since the retention time of the sensed coupled voltage on the Center MISTD shows little degradation when affecting by the above-mentioned factors, it has potential in being utilized as memory characteristic. Devices with oxide thickness smaller than 26Å was proposed for the prolonged transient phenomenon and the operations of the proposed MIS memory cell are demonstrated. The proposed memory cell shows decent retention time of 5.3s and power consumption of only 36.16pW due to limited saturation current.

口試委員會審定書……………………………………………………………………...#
誌謝……………………………………………………………………………………....I
摘要……………………………………………………………………………………..II
Abstract………………………………………………………………………………..III
Contents……………………………………………………………………………….IV
Figure Captions……………………………………………………………………….VI
Chapter 1 Introduction……………………………………………………………..1
1.1 Thesis Organization………………………………………………………….2
1.2 Fundamentals of MIS(p) Tunnel Diode……………………………………..3
1.2.1 Deep Depletion and Current Saturation Mechanism…………………4
1.2.2 Effective Schottky Barrier Height Modulation Effect………………...6
1.2.3 Thickness Dependency of Forward and Reverse Current……………7
1.2.4 Fringing Field Effect on MIS(p) Tunnel Diode………………………..8
1.3 Role of Surrounded Coupling Electrode……………………………………8
1.4 Electrical Determination of Oxide Thickness……………………………..10
1.5 Summary……………………………………………………………………12
Chapter 2 Transient Current Behavior Induced by Deep Depletion of Surrounded Coupling Electrode.......................................................19
2.1 Introduction…………………………………………………………………20
2.2 Experimental………………………………………………………………..21
2.3 Results and Discussion……………………………………………………...22
2.3.1 Voltage Decay Behavior of Ring MISTD…………………………….22
2.3.2 Transient Current Induced on Center MISTD………………………24
2.3.3 Effect of Oxide Thickness on Induced Transient Current…………...25
2.3.4 Effect of Coupling Gap Width on Induced Transient Current …….27
2.3.5 Effect of Trapped Charges on Induced Transient Current…………28
2.4 Summary……………………………………………………………………29
Chapter 3 Coupled Voltage Retention Behavior Induced by Deep Depletion of Surrounded Coupling Electrode……………………………………...39
3.1 Introduction…………………………………………………………………40
3.2 Experimental………………………………………………………………..40
3.3 Results and Discussions…………………………………………………….41
3.3.1 Coupled Voltage Retention on Center MISTD………………………41
3.3.2 Effect of Oxide Thickness on Coupled Voltage Retention…………..42
3.3.3 Effect of Coupling Gap Width on Coupled Voltage Retention………42
3.3.4 Effect of Trapped Charges on Coupled Voltage Retention………….43
3.3.5 Memory Application…………………………………………………..44
3.4 Summary……………………………………………………………………45
Chapter 4 Conclusion and Future Work…………………………………………53
4.1 Conclusion…………………………………………………………………..54
4.2 Future Work………………………………………………………………...55
Appendix Frequency Multiplier Utilizing Coupled MIS- Tunneling Diodes….59
REFERENCES………………………………………………………………………..71

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