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研究生:楊柏益
研究生(外文):Bo-Yi Yang
論文名稱:自動化圖樣至程式轉換方法應用於軟體自我測試
論文名稱(外文):Automatic Pattern-to-Program Conversion Methodology for Software-Based Self-Test
指導教授:黃俊郎黃俊郎引用關係
指導教授(外文):Jiun-Lang Huang
口試委員:李進福黃炫倫
口試委員(外文):Jin-Fu LiXuan-Lun Huang
口試日期:2020-08-14
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:45
中文關鍵詞:軟體自我測試模式到程序轉換方法測試樣板功能約束轉態延遲錯誤超大型積體電路測試
外文關鍵詞:Software-Based Self-TestPattern-to-Program ConversionTest TemplateFunctional ConstraintTransition Delay FaultVLSI Testing
DOI:10.6342/NTU202003962
相關次數:
  • 被引用被引用:0
  • 點閱點閱:192
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:1
軟體自我測試(Software-Based Self-Test)由於具有在線測試和功能性測試的特性,使得其在近幾年引起了研究人員的注意。在本論文中,我們提出了一種有效的將全掃描鏈測試圖樣轉換為測試程式之轉換方法,以幫助生成可偵測老化引起的延遲故障的高質量測試程序。該方法利用指令序列來實現自動測試圖樣產生器(Automatic Test Pattern Generation)所產生的故障檢測狀態,因此可以在處理器的操作模式下執行延遲故障測試。此外,我們提出了一個基於管道設計且適用於所有模組的測試程序樣板。同時,我們也使用基於指令集架構(Instruction Set Architecture, ISA)產生的ATPG約束,有助於提高將測試圖樣轉換為指令時的成功率,並使故障檢測狀態更易於實現。
通過這種方法,我們可以獲得測試程序,這些程序可以在最先進的晶片中快速檢測出老化引起的時序違規,而無需額外的硬體花費,並且讓攸關生命安全的汽車與醫療電子系統在正常操作模式下便能進行延遲故障自我測試。
Software-based self-test (SBST) has drawn researchers’ attention in recent years due to its capability of enabling on-line testing in functional mode. In this thesis, we proposed an efficient pattern-to-program conversion methodology to generate high-quality test programs for aging-induced delay faults. This methodology utilizes instruction sequences to realize fault detection state generated by automatic test pattern generation (ATPG). Therefore, delay fault test can be executed in operating mode of a processor. Additionally, a module-independent template based on pipeline design is proposed and ISA-based ATPG constraints are utilized to improve the pattern-to-program conversion efficiency.
With the proposed methodology, test programs that can detect the aging-induced timing violations in state-of-the-art chips can be executed without additional hardware overhead in the functional mode for life-critical, medical and automotive electronics.
口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii
Chapter 1 Introduction 1
1.1 Limitations of conventional manufacturing test 1
1.2 Built-in self-test (BIST) 2
1.3 Software-based self-test (SBST) 3
1.4 Motivation and previous work 5
1.5 Contribution 6
1.6 Organizations of the Thesis 6
Chapter 2 Preliminaries 7
2.1 Aging effect 7
2.2 Delay fault testing 8
2.3 Software-based delay fault testing 10
2.4 MIPS Instruction set architecture (ISA) 10
2.5 Pipeline design and in-order execution 12
Chapter 3 Proposed methodology 13
3.1 Software-based test program generation 13
3.2 Automatic constraint generation 14
3.3 Pattern-to-program conversion 18
3.3.1 Pattern generation using LoC 19
3.3.2 Module-independent template 20
3.3.3 Example of template execution 23
Chapter 4 Experiment result 32
4.1 Experiment setup 32
4.2 Fault coverage of PUT with 20 iterations 33
4.3 Run time analysis 36
4.4 Conversion efficiency 38
4.5 Discussion 39
Chapter 5 Conclusion and future work 41
5.1 Conclusion 41
5.2 Future work 42
REFERENCE 43
[1]Y. H. Chang, "Simulation-Based Test Patterns to Program Converter for Software-Based Self-Test," M.S. thesis, National Taiwan University, Taipei, Taiwan, 2019.
[2]R. F. Yeh, "Simulation-Based Functional Constraint Extraction for Software-Based Self-Testing," M.S. thesis, National Taiwan University, Taipei, Taiwan, 2019.
[3]T. H. Lin, "Software-Based Self-Test for Aging Defect Detection," M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018.
[4]T. H. Li, "A Flexible Hybrid Fault Simulator for Software-Based Self-Test," M.S. thesis, National Taiwan University, Taipei, Taiwan, 2017.
[5]J. Abraham, U. Goel and A. Kumar, "Multi-cycle sensitizable transition delay faults," 24th IEEE VLSI Test Symposium, Berkeley, CA, 2006, pp. 6 pp.-313.
[6]M. Yoshimura, H. Ogawa, T. Hosokawa and K. Yamazaki, "Evaluation of transition untestable faults using a multi-cycle capture test generation method," 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 2010, pp. 273-276.
[7]G. Bhargava, D. Meehl and J. Sage, "Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns," IEEE International Test Conference, Santa Clara, CA, 2007, pp. 1-7.
[8]P. Bernardi et al., "On the in-field functional testing of decode units in pipelined RISC processors," IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, 2014, pp. 299-304.
[9]K. Kambe, M. Inoue and H. Fujiwara, "Efficient template generation for instruction-based self-test of processor cores," 13th Asian Test Symposium, Kenting, Taiwan, 2004, pp. 152-157.
[10]N. Hage, R. Gulve, M. Fujita and V. Singh, "On Testing of Superscalar Processors in Functional Mode for Delay Faults," 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017, pp. 397-402.
[11]P. Bernardi et al., "On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors," 14th International Workshop on Microprocessor Test and Verification, Austin, TX, 2013, pp. 52-57.
[12]T. Lu, C. Chen and K. Lee, "Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 3, pp. 516-520, March 2011.
[13]M. S. Vasudevan, S. Biswas and A. Sahu, "RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing," 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), Delhi, NCR, India, 2019, pp. 112-117.
[14]CíceroNunes, Paulo F.Butzen, André I.Reis, Renato P.Ribas, “BTI, HCI and TDDB aging impact in flip–flops,” in Microelectronics Reliability, vol. 53, issues 9–11, pp. 1355-1359, September–November 2013.
[15]S. S. Sapatnekar, "What happens when circuits grow old: Aging issues in CMOS design," International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2013, pp. 1-2.
[16]M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan and S. Ravi, "Systematic software-based self-test for pipelined processors," 43rd ACM/IEEE Design Automation Conference, San Francisco, CA, 2006, pp. 393-398.
[17]A. Riefert, L. Ciganda, M. Sauer, P. Bernardi, M. S. Reorda and B. Becker, "An effective approach to automatic functional processor test generation for small-delay faults," Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2014, pp. 1-6.
[18]G. Ayers, A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. (Old University of Utah XUM archive), 2014, from https://github.com/grantae/mips32r1_xum
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