臺灣博碩士論文加值系統

隨著新一代產品的推出，指令集架構也跟著做修改甚至大幅翻新，像是RISC-V基於原有的RISC原則開發出的開源指令集架構。
而不管是開發新的架構或者對於嵌入式系統的編譯器後端移植，
目前大多會以LLVM來處理，所以使用LLVM開發編譯器後端的效率與通用性是個值得探討的議題。
本論文提出利用LLVM TDBlock圖形化介面工具，並在原有之整數指令集的基礎下，擴充了32與64位元的原子指令，乘法指令以及壓縮指令。其主要機制為拉取程式方塊，以圖形化的方式來將複雜的指令描述檔案，依照RISC-V指令規格書能夠將指令描述檔案產生出來。
最後本論文以此圖形介面工具擴充RISC-V指令架構，描述指令資訊；並進行各種測試來確認性能與準確性。

With the introduction of a new generation of products, the instruction set architecture has also been modified or even significantly refurbished, such as the open source instruction set architecture
developed by RISC-V based on the original RISC principles. Whether it's developing a new architecture or a compiler backend port for embedded systems, most of them are currently handled by LLVM, so using LLVM to develop the efficiency and versatility of the compiler backend is a topic worth exploring.

This paper proposes to use the LLVM TDBlock graphical interface tool, and expand the 32- and 64-bit atomic instructions, multiplication instructions and compression instructions based on the original integer instruction set. The main mechanism is to pull the program block, graphically describe the complex instruction file, and the regular format can be generated the instruction description file according to the RISC-V instruction specification.

Finally, this paper uses the graphical interface tool to expand the RISC-V instruction architecture, describe the instruction information, and conduct various tests to confirm the performance and accuracy.

摘要 IV
ABSTRACT V
致謝 VI
目錄 VII
圖目錄 VII
第一章 序論 1
1.1研究背景 1
1.2研究動機 1
1.3研究目的 2
1.4研究方法 2
1.5論文架構 3
第二章 文獻回顧 4
2.1 LLVM 4
2.2 LLVM Backend 6
2.2.1 LLVM後端流程 6
2.2.2 TableGen 7
2.3 LLVM TDBlock 9
2.4 RISC-V 11
第三章 方法 12
3.1 概念 12
3.2 擴充指令集Target Description實作 12
3.2.1 Multiplication Instruction Set 13
3.2.2 Atomic Instruction Set 22
3.2.3 Compression Instruction Set 29
第四章 實驗結果 35
4.1 實驗環境 35
4.2 執行測試 35
第五章 結論與未來展望 39
5.1 結論 39
5.2 未來展望 39
參考文獻 40

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