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研究生:江衍坊
研究生(外文):Yan-Fang Chiang
論文名稱:以無接面金氧半場效電晶體觸發之薄膜絕緣閘極雙極性電晶體
論文名稱(外文):Thin Film Insulated-Gate Bipolar Transistor Triggered by Junctionless MOSFET
指導教授:莊敏宏
指導教授(外文):Miin-Horng Juang
口試委員:徐世祥張勝良
口試委員(外文):Shih-Hsiang HsuSheng-Lyang Jang
口試日期:2020-06-15
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:41
中文關鍵詞:功率元件絕緣閘極雙極性電晶體金氧半場效電晶體無接面
外文關鍵詞:power deviceIGBTtrenchjunctionlessInsulated-Gate Bipolar TransistorMOSFET
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近年來,由於電子產品以及電力交通工具的蓬勃發展,使得功率積體電路的應用越來越廣。絕緣閘極雙極性電晶體(Insulated Gate Bipolar Transistor,IGBT)同時具有高電流與高崩潰電壓,是應用在功率積體電路的最佳元件之一。因此本文針對橫向絕緣閘極雙極性電晶體(LIGBT)進行研究與模擬。然而傳統的絕緣閘極雙極性電晶體面電路操作時會有閂鎖(latch-up)的問題。為了解決閂鎖(latch-up)問題,在本研究中,移除傳統元件中的P型井(P-well),利用無接面金氧半場效電晶體(Junctionless MOSFET)取代傳統金氧半場效電晶體,來避免寄生雙極性電晶體導通,進而改善閂鎖(latch-up)的問題。然而無接面金氧半場效電晶體會使元件的耐壓能力下降,因此本研究使用溝渠式閘極來薄化無接面電晶體的通道以維持耐壓能力。與傳統絕緣閘極雙極性電晶體相比,無接面金氧半場效電晶體有更低的導通阻抗。為了使元件的應用範圍更廣泛,本研究以調整元件厚度及通道厚度,來達到更好的導通特性;並在閘極施加負篇壓和調整源極厚度來達到更好的耐壓能力。因此以無接面金氧半場效電晶體觸發之絕緣閘極雙極性電晶體避免閂鎖(latch-up)的問題,而且有更好的導通能力以及耐壓能力。
In recent years, due to the rapid development of electronic products and electric vehicles, the application of power integrated circuits has become more extensive. As insulated gate bipolar transistor (IGBT) can support both high current and high breakdown voltage, it is one of the best devices used in power integrated circuits. Hence, this thesis will concentrate on research and simulation of insulated gate bipolar transistor (IGBT). However, conventional IGBTs usually encounter latch-up problem during circuit operation. As a result, P-well is removed in conventional power devices. In this thesis, a conventional MOSFET was replaced by junctionless MOSFET to avoid trigger of parasitic PNPN transistor. However, junctionless MOSFET would diminish break-down voltage. To maintain the blocking voltage of the device, a trench gate region is designed to thin the channel region of junctionless transistor. Compared with conventional MOSFETs, junctionless MOSFET exhibits lower on-state resistance. In addition, thicken the channel thickness of the device to reach better on-state characteristic to make the device broadly applicable. Moreover, we applied a negative bias on gate and made the source region thicker to improve break-down voltage of the device. As a result, insulated-gate bipolar transistor triggered by junctionless MOSFET can alleviate latch-up problem while demonstrating both excellent on-state and voltage withstanding characteristics.
摘要 i
Abstract ii
致謝 iii
Contents iv
Figure Contents v
Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Conventional power device 1
1-2-1 Conventional power MOSFET 2
1-2-2 Conventional IGBT 3
1-2-3 Latch-up 3
1-3 Device operation 4
1-3-1 Off-state 4
1-3-2 On-state 5
Chapter 2 Device fabrication 6
2-1 The conventional Power MOSFET 6
2-2 The conventional IGBT 7
2-3 The junctionless Power MOSFET 8
2-4 The junctionless IGBT 9
Chapter 3 Results and discussion 11
3-1 Conventional power device 11
3-1-1 Off-state characteristic 12
3-1-2 On-state characteristic 13
3-2 Junctionless power device 14
3-2-1 Off-state characteristic 15
3-2-2 On-state characteristic 16
3-3 Differences between convention and junctionless power device 17
3-3-1 Off-state characteristic of power MOSFET 17
3-3-2 Off-state characteristic of IGBT 18
3-3-3 On-state characteristic of IGBT 19
3-4 Characteristic of power MOSFET and IGBT 19
3-5 Device parameters adjustment 20
3-5-1 Device concentration adjustment 20
3-5-2 Device thickness adjustment 21
3-5-3 Drift region thickness adjustment 23
3-5-4 Source region thickness adjustment 24
3-5-5 Channel thickness adjustment 25
Chapter 4 Conclusion 30
Reference 31
[1] B. J. Baliga, “An overview of smart power technology,” IEEE Transactions on Electron Devices, vol.38, pp. 1568 – 1575, 1991.

[2] A. L. Robinson, D. N. Pattanayak, M. S. Adler, B. J. Baliga, and E. J. Wildi, “Lateral insulated gate transistors with improved latching characteristics,” IEEE Electron Device Letters, vol.7, pp. 61 – 63, 1996.


[3] Jun Cai, Keng Foo Lo, and J. K. O. Sin, “A latch-up immunized lateral trench-gate conductivity modulated power transistor,” Proc. of the 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, pp. 168 – 172, 1999.

[4] T. Ogura “Recent technical trends, and future prospects of IGBTs and power MOSFETs,” Proceedings of the International Power Electronics Conference, pp. 2068 – 2073, 2014.

[5] M. H. Chang, and P. Rutter “Optimizing the trade-off between the RDS (on) of power MOSFETs and linear mode perfomance by local modification of MOSFET gain,” Proceedings of the International Symposium on Power Semiconductor Devices and ICs, pp. 379 – 382, 2016.

[6] C. Toechterle, F. Pfirsch, C. Sandow, and G. Wachutka "Analysis of the latch up process and current filamentation in high-voltage trench-IGBT cell arrays, "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices, pp. 296 – 299, 2013.

[7] T. Trajkovic, N. Udugampola, V. Pathirana, G. Camuso, F. Udrea, and G. Amaratunga "800V lateral IGBT in bulk Si for low power compact SMPS applications," Proceedings of the International Symposium on power Semiconductor Devices & IC's, pp. 401 – 404, 2013.

[8] S. Takahashi, A. Akio, Y. Youichi, S. Satoshi, and N. Norihito "Carrier-storage effect and extraction-enhanced lateral IGBT (E 2 LIGBT): A super-high speed and low on-state voltage LIGBT superior to LDMOSFET," Proceedings of the International Symposium on Power Semiconductor Devices and ICs, pp. 393 – 396, 2012.

[9] M. R. Simpson, P. A. Gough, F. I. Hshieh, and V. Rumennik, “Analysis of the lateral insulated gate transistor,” Proc. International Electron Devices Meeting, vol.31, pp. 740 – 743, 1985.

[10] J. K. O. Sin, and S. Mukherjee, “Analysis and characterization of the segmented anode LIGBT,” IEEE Transactions on Electron Devices, vol.40, pp. 1300 – 1306, 1993.

[11] C. Toechterle, F. Pfirsch, C. Sandow, and G. Wachutka "Analysis of the latch up process and current filamentation in high-voltage trench-IGBT cell arrays, "Proceedings of the International Conference on Simulation of Semiconductor Processes and Devices, pp. 296 – 299, 2013.
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