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研究生:Bandi Lavanya
研究生(外文):BANDI LAVANYA
論文名稱(外文):Study of UHV-LDMOS Electrical Characteristics with Linear P-Top Technology by using Taurus and Fully Ion-Implantation Process
指導教授:宋昱霖
指導教授(外文):YU-LIN SONG
口試委員:蔡坤諭劉建豪宋昱霖
口試委員(外文):KUEN-YU TSAICHIEN-HAO LIUYU-LIN SONG
口試日期:2020-07-15
學位類別:碩士
校院名稱:亞洲大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:36
外文關鍵詞:1200V UHV LDMOSLinear Boron SegmentationEpitaxy layerRESURFPeak Electric FieldOn resistanceBVD
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The UHV LDMOS stands for: (Ultra High Voltage Laterally Diffused Metal-Oxide Semiconductor). In this thesis, electrical characteristics of 1200V ultra high voltage LDMOS with a linear P-Top (boron segmentation) technology by using fully ion-implantation process is developed and simulated successfully. The proposed fully ion-implantation can achieve a low specific on-resistance below 395 mΩcm2 while keep up a breakdown (BVD) voltage of 1230 Volts. Attribute of this device is the linear boron segmentation based on an optimization of n-drift doping outline according to triple RE-SURF theory. The epitaxial layer of LDMOS is restored by a Triad (Triple) Phosphorus Ion Implantation to achieve better electrical results.
Triple Phosphorus ion implantation shows the limiting of the electric peak field (EF) from 2.6e5 V/cm - 2.3e5 V/cm when compared to epitaxial film UHV LDMOS. This implement can eliminate Threshold voltage (Vth) photo masking and ion propagation (implantation) in manufacturing process. We have proactively performed sensitivity test to check the sustainability of the device and compared with epitaxy layer performance.







TABLE OF CONTENTS
CHAPTER 1 ............................................................................................................................... 1-5
INTRODUCTION...................................................................................................................... 1-2
1.1 History of Power Devices ......................................................... 3
1.2 Motivation ................................................................................................................................. 4
1.3 Outline....................................................................................................................................... 5
CHAPTER 2 ............................................................................................................................. 6-11
INTRODUCTION ABOUT UHV LDMOS WITH AND WITHOUT EPIATXY LAYER AND PRINCIPLES OF LDMOSFET ...................................................................................................... 6
2.1 Ultra High Voltage Operation .............................................................................................. ….6
2.2 Structure and Operation of LDMOS .................................................................................... ….7
2.3 LDMOS with and Without Epitaxy Layer………………………………………………………………………………………...8-9
2.4 RESURFLDMOSFET……………………………………………………………….............10
2.5 Zener Breakdown…………………………………………………………………………....11
2.6 On-Resistance of LDMOSFET .......................................................................................... ….11
CHAPTER 3 ........................................................................................................................... 12-16
ANALYSIS AND DESIGN OF HIGH VOLTAGE POWER LDMOS USING LINEAR P-TOP TECHNOLOGY WITH TRIPLE RESURF TECHNOLOGY………………………………….12
3.1 Flat region of proposed 1200V LDMOS ........................................................................... 12-13
3.2 Electrical performance of LDMOS without Epitaxy Device ……………………………14-16
3.3 Conclusion ......................................................................................................................... ….16
iii
CHAPTER 4…………………………………………………………………………………17-20
SENSITIVITY TEST BY CHANGING DRIFT LENGTH AND P-TOP DOPING………...17-18
4.1 Sensitivity Test by Changing P-top Dose .......................................................................... ….19
4.2 Sensitivity Test by Changing Drift Length ........................................................................ ….20
4.3 Conclusion .............................................................................................................................. 20
CHAPTER 5…………………………………………………………………………………21-23
COMPARING WITH AND WITHOUT EPITAXY LAYER ELECTRIC FIELD AND BREAKDOWN VOLTAGE FOR SILICON LIMIT LINE…………………………………….21
5.1 Electric Field Performance for with and without Epitaxy Layer ………………………...21-22
5.2 Breakdown Voltage Compared with Silicon Limit Line……………………………….........23
5.3 Conclusion .............................................................................................................................. 24
CHAPTER 6 ................................................................................................................................ 25
CONCLUSION…………………………………………………………………………………25
REFERENCES……………………………………………………………………………...26-27

LIST OF FIGURES
Fig 1 Fundamental atomic structure of Boron, Silicon and Phosphorus……………………………1
Fig 2. Basic atomic structure……………………………………………………………………....2
Fig 3 Power Devices Struggle and Evaluation…………………………………………………….3
Fig 4(a) Basic MOSFET structure………………………………………………………………....6
Fig 4 (b) Basic LDMOS structure………………………………………………………………….6
Fig. 5 Cross-section of a LDMOS Structure……………………………………………………….7
Fig.6 Cross-sectional view of the 1200V with epitaxy layer device……………………………......8
Fig.7 Cross-sectional view of triple phosphorous implantation UHV LDMOS……………………9
Fig 8 Lateral RESURF Structure at Full Depletion………………………………………………10
Fig. 9 Ideal MOSFET specific resistance vs. Breakdown Voltage curve…………………………11
Fig. 10 The cross-sectional view of proposed structure………………………………………….12
Fig 11 P-top Linearity Masking Design………………………………………………………….13
Fig 12 Doping Profile for Linear P-top…………………………………………………………...13
Fig 13 Breakdown Voltage for LDMOS without Epitaxy Layer…………………………………14
Fig 14 IDVD Curve ……………………………………………………………………………...15
Fig 15 Threshold Voltage and On-resistance…………………………………………………….16
Fig 16. P-top dose vs. BVD and Ron………………………………………………………………18
Fig 17. Drift length sensitivity vs. Breakdown and On-resistance……………………………......20
Fig 18. Electric Peak Field Distribution………………………………………………………….21
Fig 19. Ideal silicon limit line……………………………………………………………………23
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[2]B. J. Baliga, “Power Semiconductor Devices,” ISBN 0-534-94098-6. Devices, Vol. 38, pp.1568-1575, 1991.
[3]SHEU, Gene, and Ching-Yi Huang. "A study of low cost 1200V linear P-top LDMOS device." 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017
[4]Lavanya BANDI, A. Hemanth, B. H. Kumar, A. C. Wijaya and G. SHEU, "Fully Ion-Implanted 1200V LDMOS with Linear P-Top Technology," 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW), YILAN, Taiwan, 2019, pp. 1-2,
DOI: 10.1109/ICCE-TW46550.2019.8991849.
[5]A. W. Ludikhuize, ``A Review of RESURF Technology,'' Proc. Intl. Symposium Power Semiconductor Devices Integrated Circuits, pp. 11-18, and 2000.
[6]Appels, J. A. "THIN LAYER High-VOLTAGE DEVICE." Phillips J. Res. 35 (1980): 1-13.
[7]T. Efland, S. Malhi, W. Bailey, O. K. Kwon, and W. T. Ng, ``An Optimized RESURF LDMOS Power Device Module Compatible with Advanced Logic Processes,'' Proc. Intl. Electron Devices Meeting, pp. 237-240, 1992
[8]Fang Jian, Yi Kun, Li Zhaoji, et al. On-state breakdown model for high voltage RESUEF LDMOS. Chinese Journal of Semiconductor, 2005, 26 (3):437
[9]Z.Parpia, C.A.T.Salanma. Optimization of RESURF LDMOS transistors: An Analytical Approach.IEEE Trans.Elect.Dev.1990, 12(3):789-795
[10]Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances, University of California, Berkeley - 2002.
[11]Jin He, et al “Linearly graded doping drift region: a novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances” Volume 17 Number 7 Semiconductor Science and Technology, 18 June 2002.
[12]Tam, David, and E. Segundo. "New 1200V Integrated Circuit Changes the Way 3-Phase Motor Drive Inverters Are Designed." IR Technical Paper, July 2008 (2008).
[13]Choi, Yongcheol, Changki Jeon, and Minsuk Kim. "Design and process considerations for 1200V HVIC technology." 2009 21st International Symposium on Power Semiconductor Devices & IC's. IEEE, 2009.
[14] Nakagawa, Akio, Yusuke Kawaguchi, and Kazutoshi Nakamura. "Achieving material limit characteristics in silicon power devices." 2007 International Workshop on Physics of Semiconductor Devices. IEEE, 2007.
[15]Fang Jian, et al “Realization of a novel 1200 V VLD double RESURF LDMOS with n-bury layer” CHINESE JOURNAL OF SEMICONDUCTORS Vol .26 No. 3 Mar. ,2005.
[16]Sunitha HD et al” Reduced Surface Field Technology For LDMOS: A Review” Volume 4, Issue 6, International Journal of Emerging Technology and Advanced Engineering, June 2014.
[17]S.M. Sze “Semiconductors Devices Physics and Technology”, AT & TBELL Laboratories, 1985, pp.384, 410- 411
[18]Fang Jian, et al “Realization of a novel 1200 V VLD double RESURF LDMOS with n-bury layer” CHINESE JOURNAL OF SEMICONDUCTORS Vol .26 No. 3 Mar. ,2005.
[19]https://www.researchgate.net/publication/327649089_An_Innovated_80V-100V_High-Side_Side-Isolated_N-LDMOS_Device.

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