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研究生:陳柏勳
研究生(外文):CHEN, PO-HSUN
論文名稱:考量人力限制於半導體廠之動態投料法則設計
論文名稱(外文):Dynamic Dispatching Rule Considering Finite Workforce for Semiconductor Wafer Fabrication Process
指導教授:邱創鈞邱創鈞引用關係
指導教授(外文):CHIOU, CHUANG-CHUN
口試委員:林水順翁紹仁邱創鈞
口試日期:2020-06-24
學位類別:碩士
校院名稱:東海大學
系所名稱:工業工程與經營資訊學系
學門:工程學門
學類:工業工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:37
中文關鍵詞:投料法則有限人力產能規劃系統模擬
外文關鍵詞:Dynamic DispatchingFinite WorkforceProduction ManagementSimulation
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工作調度、投料及派工是半導體晶圓製造工程中不可或缺的重要角色。工程師致力改善這些項目,以縮短在製品數量、提升生產良率,同時也為了達到更高的達交率。已有許多研究著重在探討生產線平衡及在製品數量的控制,以便了解何種派工或投料法則能為既有的生產線帶來更大的效益。但這些研究較少考量人力對於投料及派工法則的影響。若生產線中仍以人力進行搬運、上下料及備料的作業,可以稱該產線為「半自動生產線」,其人力作業未必能提高產品價值,卻會影響產品生產週期及物品在產線中流動的狀況。在這樣的環境之下,有限人力可能會帶來機台及物品的等待,進而影響系統資料的可信度。這篇研究設計動態投料法則,並應用系統模擬分析各種投料法則在「無限人力」及「有限人力」的環境下。首先探討有限人力對於半自動生產線的影響,其次提供產線基於「無限人力」及「有限人力」的投料標準及決策流程。個案研究結果顯示:生產效益會因有限人力的限制下降,生產週期時間也會因此增加;導入本論文所提供之動態投料法則後能有5%的改善,且DDR法則能控制80%的料件在不同人力限制時有更穩定的生產週期時間。
Job dispatching plays an important role in semiconductor wafer fabrication processes, the goal is to decrease work-in-process (WIP), have a better yield rate, and to satisfy the due date. Most researches focus on how line balancing and WIP controlling effect the decision flow while dispatching, however, not every wafer fab process is fully automated. Factories that required operators to handle materials or works are considered semi-automated, and the finite workforce may cause materials waiting for operators to move or to monitor. As a result, a dynamic dispatching rule considering finite workforce is proposed for semi-automated wafer fab line. A case study is demonstrated by simulation to present the conclusion. The results show that finite workforce will decrease throughput amount and increase cycle time. By the dynamic dispatching rule proposed in this study, both throughput and cycle time have significant improvements.
目錄
摘 要 i
ABSTRACT ii
致謝詞 iii
目錄 iv
表目錄 v
圖目錄 vi
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 研究問題 2
1.4 研究目的 3
1.5 研究流程 3
第二章 文獻探討 5
2.1 半導體廠投料法則相關文獻 5
2.2 探討人力的相關文獻 8
第三章 研究方法 10
3.1 建立模擬環境 10
3.2 變數與參數說明 10
3.3 無限人力與有限人力之投料決策流程 11
第四章 研究結果與發現 19
4.1 現況及模型建立說明 19
4.2 建立模型限制及程式碼 22
4.3 參數及有限人力的調整 22
4.4 模型確認與驗證 23
4.5 模擬結果 23
第五章 結論與未來研究方向 34
5.1 結論 34
5.2 未來研究方向與建議 35
參考文獻 36


參考文獻
中文部分
翁紹仁、Savory, P.。系統模擬與Simul8教戰手冊。高雄市:阜盛文教。
英文部分
1.Arturo, M. & Meyuhas, A.,(2016) Fab labor productivity improvement through a combined modeling approach. 2016 International Symposium on Semiconductor Manufacturing (pp.1-5). Tokyo
2.Balle, F. & Balle, M. (2006). Feel the force of flexible manpower. Manufacturing Engineer., 84(6), 20-25.
3.Bergmann, S., Feldkamp, N., & Strassburger, S. (2015). Approximation of dispatching rules for manufacturing simulation using data mining methods. 2015 Winter Simulation Conference (pp.2329-2340.), Huntington Beach, CA.
4.Chen, H. Z., Liu, C., Rong, Y., & Zhu, J. (2012). Research on dynamic dispatching rule for semiconductor assembly production line. 2012 IEEE International Conference on Industrial Engineering and Engineering Management (pp.493-497). Hong Kong.
5.Cheong, W. K., Look, S. O., & Mohamed, H. (2007). Improving direct labour productivity through minimizing time wastage approach. 2007 International Symposium on Semiconductor Manufacturing (pp.1-4). Santa Clara, CA.
6.Cho, K. H., Chung, Y. H., Choung, Y. I., Park, S. C., & Kim, B. H. (2017). Two boundary based dispatching rule for on-time delivery and throughput of wafer fabs with dedication constraints. 2017 Winter Simulation Conference (pp.3555-3564). Las Vegas, NV.
7.Chung, Y. H., Kim, B. H., Seo, J. C. (2015) Reservation Based Dispatching Rule for Wafer Fab with Engineering Lots. 2015 Proceedings of the 2015 Winter Simulation Conference (pp.2974-2982). Huntington Beach, California.
8.Concannon, K., Elder, M., Hindle, K., Tremble, J., Tse, S. (2007) Simulation Modeling with Simul8. Visual Thinking Int. Canada.
9.Cui, M. & Li, L. (2018). A closed loop dynamic scheduling method based on load balancing for semiconductor wafer fabrication facility. 2018 IEEE International Conference on Smart Manufacturing, Industrial & Logistics Engineering (SMILE) (pp.1-6). Hsinchu.
10.Dequeant, K., Vialletelle, P., Lemaire, P., & Espinouse, M. L., (2016, December). A literature review on variability in semiconductor manufacturing: The next forward leap to industry 4.0. 2016 Winter Simulation Conference (pp.2598-2609). Washington, DC.
11.Jaret W. H., Kerrie, N. (2002) Learning SIMUL8: The Complete Guide. Plain Vu Publishers
12.Kerk, E., Chan, C. M., (2018) Queue Time Reduction in Wafer Fab Process through Six Sigma Approach. 2018 e-Manufacturing & Design Collaboration Symposium (eMDC) (pp.1-4), Hsinchu
13.Li, L., Qiao, F., Jiang, H., & Wu, Q. (2004). The research on dispatching rule for improving on-time delivery for semiconductor wafer fab. ICARCV 2004 8th Control, Automation, Robotics and Vision Conference Vol. 1. (pp.494-498). Kunming, China.
14.Liu, C., M., Kuo, C., J., Chi, C., Y. (2006). A Dynamic Method for Optimal WIP Allocation and Control in a Semiconductor Manufacturing System. IEEE International Symposium on Semiconductor Manufacturing Conference Proveedings. (pp.61-65).
15.Park, S. C., Kim, B. H., Ahn, E., Chung, Y., & Yang, K. (2013). Fab simulation with recipe arrangement of tools. 2013 Winter Simulation Conference (pp.3840-3849). Washington, DC.
16.Yoon, S., & Jeong, S. (2018). Line balancing strategy for re-entrant manufacturing. IEEE Transaction on Semiconductor Manufacturing,31(1), 42-51.

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