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研究生:張育銓
研究生(外文):Yu-Chuan Chang
論文名稱:以次微米金氧半製程實現應用於人體通訊之低功耗接收發射器設計
論文名稱(外文):Design of Low Power Transceiver for Human Body Communication Applications in Sub-Micro CMOS Process
指導教授:施鴻源
指導教授(外文):Horng-Yuan Shih
口試委員:江正雄張家宏楊維斌陳信良
口試委員(外文):Jen-Shiun ChiangChia-Hung ChangWei-Bin YangSin-Lian Chen
口試日期:2020-01-09
學位類別:博士
校院名稱:淡江大學
系所名稱:電機工程學系博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:英文
論文頁數:61
中文關鍵詞:低功耗人體通訊收發器
外文關鍵詞:Low powerHuman body communicationTransceiver
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論文提要內容:
隨著生醫電子應用的快速發展,將晶片穿戴或植入人體用以偵測各種生理訊號或是進行藥物釋放成達到居家照護的目的將成為趨勢。由於此類晶片的電源來源為電池、體熱發電或是無線電能量收集電路,因此在其傳輸介面電路設計上最重要的要求為超低功率消耗,以達到延長使用壽命的目的。由於接收器必須長時間維持開啟狀態,因此接收器的功率消耗佔了整體功率消耗的一半以上,因此實現一超低功耗接收器可大幅延長使用時間。
本論文提出了一種適用於穿戴式裝置的低功耗人體通訊收發器。 該收發器採用UMC 0.18 µm CMOS製程。應用於穿戴式裝置時,高功率效率可使穿戴式裝置的使用時間大大提高。所提出的接收器在僅1.79 mW的功耗下實現了1 Mb / s的最大傳輸速率。因此,可以實現每接收位1.79 nJ的最小能耗。發射器在10 Mb / s的最大發射傳輸速率下消耗700μW。 因此,每個傳輸位元的最低能耗為70 pJ / bit。
As age advances, the electronic applications in the biomedical develops rapidly. It is the trend that people carry chips or implant chips into their body in order to detect a variety of physiological signals. Also, they use chips to release medicines to achieve the purpose of home care. As those chip’s power source used for the battery, the power generation of body heat or radio energy harvested circuit, therefore the most important requirements in transmission interface circuit design for ultra-low power consumption to extend the service life of purpose. Since the receiver must remain turn on for a long time, the receiver''s power consumption accounted for more than half of the overall power consumption, therefore to achieve an ultra-low power receiver can significantly extend the used time.
An low power human body communication (HBC) transceiver applied for wearable devices is presented. The transceiver is implemented in UMC 0.18 µm CMOS process. As applying for wearable devices, the high power efficiency leads to a great improvement of lift time of the wearable devices. The proposed receiver achieves a maximum data rate of 1 Mb/s under a power consumption of only 1.79 mW. Thus, minimum energy consumption per received bit of 1.79 nJ can be achieved. The proposed transmitter consumes 700 μW at the maximum transmitted data rate of 10 Mb/s. Therefore, minimum energy consumption per transmitted bit of 70 pJ/bit can be achieved.
Table of Contents
中文摘要 I
Abstract II
Table of Contents III
List of Figures V
List of Tables VII
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 ULTRA LOW POWER TRANSCEIVER CIRCUIT 4
2.1 Ultra-low power circuits design 4
2.2 Modulation schemes for ultra-low power transceivers 7
2.3 Introduction to the receiver architecture 8
2.3.1 Amplitude shift keying receiver architecture 8
2.3.2 Frequency shift keying receiver architecture 9
2.4 Introduction to the transmitter architecture 16
2.4.1 Amplitude shift keying transmitter architecture 16
2.4.2 Frequency shift keying transmitter architecture 17
2.5 Introduction to FSK modulation transmitter types 20
2.5.1 Continuous and Discontinuous FSK modulation types 20
2.5.2 Condition of Discontinuous FSK transfer to continuous FSK 22
CHAPTER 3 LOW POWER TRANSCEIVER FOR HUMAN BODY COMMUNICATION APPLICATOIN 25
3.1 Definition of BANs 25
3.2 HBC Band 25
3.3 Standardization of IEEE 802.15.6 26
3.4 Low power transceiver system architecture 29
CHAPTER 4 CIRCUIT DESIGN 32
4.1 Receiver front-end 32
4.2 Limiting amplifier 33
4.3 DLL based demodulation 34
4.3.1 Phase-frequency detector (PFD) 36
4.3.2 Charge pump 40
4.3.3 Voltage control delay line (VCDL) and replica delay line 42
4.3.4 Locking time analysis 42
4.3.5 Low power demodulator 43
4.4 Sallen-key filter 44
4.5 Transmitter 46
CHAPTER 5 MEASUREMENT RESULT 48
CHAPTER 6 CONCLUSION 54
REFERENCE 55
投稿論文 59


List of Figures
Figure 1.1 Human body communication (HBC). 2
Figure 2.1 (a) Definition of operating area of transistor, (b) Transistor''s relationship between operating speed and intrinsic gain by operating in sub-threshold region at 0.18 μm process[18]. 6
Figure 2.2 Architecture of super regenerative receiver front-end circuit [19]. 8
Figure 2.3 ASK ultra-low power wireless transmission chip circuit architecture [20]. 9
Figure 2.4 Architecture diagram of frequency to amplitude [21]. 10
Figure 2.5 Frequency-to-amplitude for demodulator use the injection locked frequency divider technology [21]. 11
Figure 2.6 Architecture diagram of Receiver demodulation circuit [21]. 11
Figure 2.7 Performance comparison diagram of ultra low power receiver [21]. 12
Figure 2.8 Architecture of demodulator by using analog mixers and delay cell [23]. 12
Figure 2.9 Architecture of DLL/PLL based demodulator [24]. 13
Figure 2.10 DLL/PLL based demodulator transient diagram [24]. 14
Figure 2.11 Architecture of demodulator using a digital circuit [25]. 15
Figure 2.12 OOK transmitter circuit [26]. 16
Figure 2.13 High performance transceiver circuit architecture [26]. 17
Figure 2.14 Transmitter modulation circuit architecture [21]. 18
Figure 2.15 Performance comparison diagram of ultra low power transmitter [21]. 19
Figure 2.16 Continuous FSK modulation[27]. 20
Figure 2.17 Discontinuous FSK modulation [27]. 21
Figure 2.18 Continuous FSK transmitter using digital calibration [28]. 22
Figure 3.1 802.15.6 HBC emission signal Spectrum Mask. 28
Figure 3.2 The reference transmitter architecture proposed by IEEE 802.15.6 HBC. 28
Figure 3.3 System architecture of HBC DPFSK Transceiver. 29
Figure 3.4 Direct-conversion of FSK signal (a) in frequency domain (b) in time domain. 30
Figure 3.5 Signals at (a) input of the receiver (b) output of the front-end. 31
Figure 4.1. Schematics of direct-conversion front-end. 32
Figure 4.2 Schematics of limiting amplifier. 33
Figure 4.3 Principle of demodulation (a) Data ‘1’ is received (b) Data ‘0’ is received. 35
Figure 4.4 Functional blocks of the DLL. 36
Figure 4.5 Phase detection circuit characteristic curve. 37
Figure 4.6 (a) Phase-frequency detector circuit architecture diagram (b) D flip-flop circuit diagram. 38
Figure 4.7 (a) Phase of wave A lead wave B (B) Phase of wave B lead wave A. 39
Figure 4.8 Charge pump circuit architecture diagram. 40
Figure 4.9 (a) Schematic diagram of the charge pump when charging, (b) Schematic diagram of the charge pump when discharging. 41
Figure 4.10 Schematic diagram of the voltage control delay line and delay cell. 42
Figure 4.11 Schematics of low power demodulator. 44
Figure 4.12 Schematics of sallen-key filter. 45
Figure 4.13 Simulated frequency response of the sallen-key filter. 46
Figure 4.14 Delay cell of the ring oscillator 47
Figure 4.15 Simulated output frequency of the ring oscillator.. 47
Figure 5.1 Chip micrograph. 48
Figure 5.2 Measured output signal of the transmitter under a data rate of (a) 2 Mb/s (b) 10 Mb/s. 49
Figure 5.3 (a) Measurement setup by using a human arm as transmission media. (b) Transmitted data and the received data under a data rate of 1 Mb/s. 50
Figure 5.4 (a) Measurement setup (b) picture of the measurement. 51
Figure 5.5 A string of texts transmitted between two PCs (a) screen of PC1 (transmission terminal) (b) screen of PC2 (receive terminal). 52


List of Tables
TABLE 2.1 Comparison with ASK and FSK Receiver 16
TABLE 2.2 Comparison with ASK and FSK transmitter 19
TABLE 3.1 IEEE 802.15.6 HBC data transmission rate under different applications. 29
TABLE 5.1 Performance Summary and Comparison with Other Work 53
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