本論文提出一個改善循環摺疊疊接放大器迴轉率之放大器電路，改善電路直流增益及迴轉率，使用TSMC 0.18um 1P6M CMOS 製程技術來實現電路晶片。此論文提出的放大器是利用高增益電路、Shunt Current Sources及Damping Factor來提升電路的直流增益、增益頻寬以及電壓迴轉率，模擬結果顯示本論文所提出放大器較優於傳統循環摺疊疊接放大器。此電路以1.8V供應電壓與5pF負載電容來模擬放大器電路，模擬結果顯示所該放大器效能可達到直流增益為88.56dB，電壓迴轉率為65.7V⁄μs，增益頻寬為138.12MHz，相位邊限為〖 68.7〗^°。

This study presented a slew rate enhancement for recycling folded cascode amplifier and it improved the DC gain and slew rate than traditional recycling folded cascode amplifier. The proposed circuit has been implemented and verified using TSMC 0.18um 1P6M CMOS process with 1.8V power supply and 5pF capacitor load. This circuit simulation results showed that the proposed circuit achieve better preformance than traditional recycling folded cascade structure. This circuit enhances the dc gain, gain bandwidth, and slew rate by applying the high-gain circuit, shunt current sources , and damping factor. From the simulation results, the proposed amplifier can achieve 88.56dB DC gain, 65.7V⁄μs slew rate, 138.12MHz gain-bandwidth and 〖68.7〗^° phase margin.

摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
第二章 放大器電路架構基礎理論 6
2.1 運算放大器架構與簡介 6
2.2 放大器電流源種類與架構原理 9
2.2.1 基本電流鏡(Basic current mirror) 9
2.2.1 疊接電流鏡(Cascode current mirror) 10
2.3 運算放大器規格參數與特性 13
2.3.1 直流增益(DC gain) 13
2.3.2 相位邊限(Phase margin, PM) 14
2.3.3 單位增益頻率(Unity-gain frequency, UGF) 15
2.3.4 電壓迴轉率(Slew rate, SR) 16
2.3.5電源供應抑制比(Power supply rejection ratio, PSRR) 17
2.4 兩級放大電路 17
2.4.1 相位邊限(Phase margin, PM) 21
2.4.2 單位增益頻率(Unity-gain frequency, UGF) 21
2.4.3 電壓迴轉率(Slew rate, SR) 22
2.5 運算放大器架構比較與應用 23
2.6 循環摺疊疊接放大器架構原理 25
第三章 改善循環摺疊疊接放大器迴轉率之設計 29
3.1 改善迴轉率之循環摺疊疊接放大器 29
3.2 巢式米勒補償法 31
3.3 改善迴轉率之循環摺疊疊接放大器電路架構與原理 34
第四章 電路模擬結果與分析 41
4.1 改善迴轉率之循環摺疊疊接放大器表示模型模擬與分析 41
4.2 電路佈局 49
4.3 效能參數比較 50
第五章 結論 51
參考文獻 52
附錄 : 口試委員提問 55

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