臺灣博碩士論文加值系統

近年來許多可攜式或穿戴式電子產品在設計上都朝向短小輕薄之目標，由於這些產品皆採用電池供電設備，因此開發低功耗以延長電池壽命及體積小的電路已經成為主要的議題。低壓降穩壓器具有低雜訊和低功耗等特性，所以廣泛使用在各類電子產品中，然而，傳統的低壓降穩壓器雖能達到穩壓的效果，但卻無法同時達到低功耗以及快速的暫態響應等之需求。
本論文提出一個具有快速暫態響應的無負載電容式低壓降穩壓器，利用交叉耦合技術改善傳統運算放大器之暫態響應，進而提升低壓降穩壓器的暫態響應。本電路使用TSMC 0.18μm 1P6M CMOS 製程技術來實現，整個電路工作於1.2V供應電壓且並使用10pF負載電容來進行電路效能模擬。根據模擬結果，此電路可提供之最大輸出電流為100mA，整體直流增益可達到72.08 dB，且暫態穩定時間可達到0.28μs。

Recently, the design of many portable electronic device and wearable electronic device is aimed to small size. All of these products are battery-powered. Therefore, the development of circuits with low power consumption and small chip area has become the main issue. The conventional LDOs regulators has the characteristics of low noise and low power consumption and are widely used in many electronic products.
In this thesis, an output capacitorless low dropout regulator with fast transient response is proposed. By applying the cross-coupled technique, the transient response of the traditional operational amplifier is improved. Therefore, the transient response of the proposed low dropout regulator is improved. The low dropout regulator is implemented using TSMC 0.18μm 1P6M CMOS process and simulated with a 1.2V supply voltage. From the simulation results, this circuit can deliver a maximum load current of 100mA with a 10pF load. Moreover, it can achieve DC gain with 72.08 dB and fast transient response with 0.28μs.

摘 要 i
ABSTRACT ii
誌 謝 iii
目 錄 iv
表 目 錄 vii
圖 目 錄 viii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 3
1.3 研究方法 4
1.4 論文架構與簡介 6
第二章 無負載電容式低壓降穩壓器的基礎 7
2.1 穩壓器電路之文獻探討 7
2.2 低壓降穩壓器電路架構與應用 11
2.3 規格與特性 13
2.3.1 壓降電壓 (Dropout Voltage) 14
2.3.2 功率效率 (Power Efficiency) 16
2.3.3 靜態電流 (Quiescent Current) 17
2.3.4 電源電壓調整率 (Line Regulation) 19
2.3.5 負載調節率 (Load Regulation) 21
2.3.6 暫態響應 (Transient Response) 23
2.3.7 電源電壓抑制比 (Power Supply Rejection Ratio) 25
2.4 驅動傳輸電晶體介紹 26
2.5 傳統低壓降穩壓器電路架構 30
第三章 設計改良型無負載電容式之低壓降穩壓器 37
3.1 改良型無負載電容式之低壓降穩壓器設計流程 37
3.2 交叉耦合運算放大器之設計 39
3.2.1 運算放大器架構與簡介 39
3.2.2 交叉耦合式（Cross-Coupled, CC）誤差放大器 47
3.3 改良型無負載電容式低壓降穩壓器架構與原理 52
第四章 電路模擬結果與分析 60
4.1 改良型無負載電容式低壓降穩壓器模擬 60
4.1.1 交流分析 (Alternating Current Analysis) 61
4.1.2 直流分析 (Direct Current Analysis) 63
4.1.3 電源電壓調整率 (Line Regulation) 64
4.1.4 負載調節率 (Load Regulation) 66
4.1.5 暫態響應及穩定時間(Transient Response and Settling Time) 68
4.1.6 電源電壓抑制比 (Power Supply Rejection Ratio) 72
4.2 效能參數比較 75
4.3 晶片佈局 76
4.3.1 晶片佈局平面圖 77
4.3.2 晶片打線圖 78
4.3.3 晶片打線封裝圖 79
第五章 結論 80
參考文獻 81
附錄 89
1. 楊博惠 委員： 89
2. 林淵翔 委員： 94
3. 郭柏佑 委員： 98

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