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研究生:蕭羽芸
研究生(外文):XIAO, YU-YUN
論文名稱:應用於12位元SAR ADC之 LSIM校正演算法及晶片系統實現
論文名稱(外文):A LSIM Calibration Algorithm for 12-bit SAR ADC and Chipset Implementation
指導教授:許明華許明華引用關係
指導教授(外文):SHEU, MING-HUA
口試委員:蔡宗亨賴信志夏世昌許明華
口試委員(外文):TSAI, TSUNG-HENGLAI, SHIN-CHISHIA, SHR-CHANGSHEU, MING-HUA
口試日期:2020-07-17
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:108
語文別:中文
論文頁數:115
中文關鍵詞:逐漸逼近式類比數位轉換器LSIM校正演算法電容不匹配
外文關鍵詞:Successive Approximation Register Analog–to–Digital Converter (SAR ADC)Least Square and Iterative Methods (LSIM) digital calibration algorithmCapacitor mismatch
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本篇論文提出了一個應用於12位元逐漸逼近式類比數位轉換器(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)的最小平方與迭代法(Least Square and Iterative Methods, LSIM) 數位校正演算法以及一個含晶片的校正系統。本論文採用逐漸逼近式類比數位轉換器的架構,由於其具有低功耗、中等轉換速度與高解析度的特點,適合生醫訊號的應用,而其架構由取樣與保持電路、比較器電路、逐漸逼近式暫存器控制邏輯電路、數位類比轉換器控制邏輯電路與電容陣列式數位類比轉換器所組成。在此為達到12位元解析度,以雙端差動對輸入的架構實現,並採用有效能量開關切換的方式來降低功耗,並且改變其切換方式,以單向式切換取代傳統雙向式的切換形式,使得電容陣列式數位類比轉換器之輸出電壓能夠向下切換作逼近,用以減少數位類比轉換器電容陣列的切換次數,以及達到降低功耗的目的。
在逐漸逼近式類比數位轉換器操作中,電容陣列式數位類比轉換器的電容值不匹配(Mismatch)現象,是影響逐漸逼近式類比數位轉換器的輸出解析度的重要關鍵,故在此提出一LSIM校正演算法,來校正逐漸逼近式類比數位轉換器中的電容不匹配問題。
整合晶片使用台積電0.18微米1P6M製程實現,電源電壓為1.8伏特,晶片面積為1.2 * 1.2平方毫米,核心電路面為475.21*818.06平方微米,有效位元數為8.43位元,功耗為3.11微瓦。在取樣頻率為8.192千赫茲。輸入頻率401赫茲下,由後模擬數據校正結果顯示,在最高權重電容不匹配比例為-2 %時,LSIM校正演算法可將訊號雜訊失真比從44.27分貝校正回71.79分貝,有效位元從7.82位元校正回11.68位元。

This paper proposes a Least Square and Iterative Methods (LSIM) digital calibration algorithm applied to a 12-bit Successive Approximation Register Analog–to–Digital Converter (SAR ADC) and a calibration system containing SAR ADC chip. This paper adopts the architecture of successive approximation register analog–to–digital converter. Due to its low power consumption, medium conversion speed and high resolution, it is suitable for the application of biomedical signals. A successive approximation register analog–to–digital converter is composed of a sample–and–hold (S/H) circuit, a comparator, a successive approximation register (SAR) control logic, a digital–to–analog converter (DAC) control logic, a capacitor array digital analog converter. In order to achieve 12–bit resolution, the architecture of the input is implemented with double–ended differential. The effective energy switching is adopted to reduce the power consumption, and the traditional double–tuning switching form is replaced by the monotonic switching form. The switching mode enables the output voltage of the capacitor array digital analog converter to be switched downward to approximate, which is used to reduce the number of switching times of the capacitor array of the digital analog converter and achieve the purpose of reducing power consumption.
In the operation of the successive approximation register analog–to–digital converter, the capacitance mismatch of the capacitor array digital-to-analog converter, which is an important key affecting the output resolution of the successive approximation register analog–to–digital converter. Therefore, a LSIM digital calibration algorithm is proposed to correct the capacitance mismatch problem in the successive approximation register analog–to–digital converter.
The prototype was fabricated using TSMC 0.18–µm 1P6M CMOS process. Supply voltage is 1.8V, the chip area is 1.2 * 1.2mm2 and the core circuit area is 475.21 * 818.06μm2, the effective number of bits is 8.43-bit, and the power consumption is 3.11μW. At the sampling frequency is 8.192 kHz, the input frequency is 401 Hz, the post-simulation data calibration results show that the LSIM correction algorithm can calibrate the signal-to-noise distortion ratio from 44.27 dB back to 71.79 dB, the effective number of bits from 7.82-bit back to 11.68-bit.

摘要 i
Abstract ii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1-1 研究動機與目的 1
1-2 相關研究發展 3
1-3 整體系統與論文架構 5
第二章 SAR ADC 實現與佈局設計 7
2-1 SAR ADC架構與運作分析 7
2-2 區塊電路架構與運作分析 10
2-2-1 取樣與保持電路(Sample and Hold, S/H) 10
2-2-2 比較器電路(Comparator, CPT) 16
2-2-3 逐漸逼近式暫存器控制邏輯(SAR Control Logic) 20
2-2-4 數位類比轉換器控制邏輯(DAC Control Logic) 23
2-2-5 電容陣列式數位類比轉換器(P/N_C-Array DAC) 25
2-3 SAR ADC電路模擬結果與晶片佈局 27
2-3-1 SAR ADC前模擬(SAR ADC Pre-Simulation) 28
2-3-2 SAR ADC佈局(SAR ADC Layout) 32
2-3-3 SAR ADC後模擬(SAR ADC Post-Simulation) 39
第三章 LSIM數位校正演算法(Least Square and Iterative Methods) 43
3-1 SAR ADC電容不匹配誤差分析 43
3-2 LSIM數位校正演算法推導 45
3-3 LSIM數位校正演算法迭代次數決定 50
3-4 LSIM數位校正演算法之最小輸入資料筆數驗證 52
3-5 LSIM數位校正演算法校正結果(Matlab Simulation) 56
第四章 測試平台與實現 68
4-1 測試平台實現 68
4-1-1 互補訊號產生電路(Complementary Signal Generator) 69
4-1-2 參考電壓產生電路(Vref Generator) 71
4-2 測試平台運作 71
第五章 實測晶片結果與校正結果 75
5-1 SAR ADC晶片實測結果 75
5-2 LSIM校正後模擬數據效果與文獻比較 79
第六章 問題探討與未來展望 90
6-1 問題探討 90
6-2 總結與未來展望 94
參考文獻 96
附錄 98

參考文獻
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