臺灣博碩士論文加值系統

位元可變技術是一項尖端技術，其新穎的操作可任意擦除快閃記憶體區塊中的頁面級數據。儘管頁級擦除操作可以減輕快閃記憶體中頁面複製的性能開銷，但它也導致了新的磨損均衡問題。在這樣的問題中，快閃記憶體中同一區塊的頁面在運行期間將收到不同的寫入/擦除（P / E）週期。換句話說，儲存熱數據的某些特定頁面耐久度將很快達到上限；因此，由於快閃記憶體中頁面的磨損程度不均衡，因此位元可變的快閃記憶體壽命將縮短。因此，它成為位元可變快閃記憶體設計中的關鍵問題，並且無法通過最新的磨損均衡設計解決。為了解決快閃記憶體區塊內部頁面的磨損不均衡，本研究提出了一種考慮此類磨損均衡問題的雙相垃圾回收機制。雙相機制同時關注內部和區塊間磨損平衡問題。在區塊內部磨損均衡問題上，雙相機制通過少量位元判斷熱頁面，並限制熱頁面儲存熱數據而不犧牲存儲容量。另一方面，我們提出的機制還提出了解決方案，以最大程度地減少區塊間磨損平衡問題的頁面複製。根據實驗結果，與最新的垃圾回收機制相比，我們的雙相機制可以將位元可變的快閃記憶體壽命延長兩到四倍。

Bit-alterable flash memory is a cutting-edge technology that enables a novel operation, called page-level erase operation, to erase a flash page within a block arbitrarily. Though the page-level erase operation can ease the overhead of the live-page copying during a garbage collection process, it also introduces a new wear-leveling problem. In such the problem, flash pages within the same block will receive different program/erase (P/E) cycles during runtime. Some specific pages storing hot data will be worn out soon; therefore, the lifespan of the bit-alterable flash memory will be short due to the uneven worn out of flash pages. Consequently, it becomes a critical issue with the bit-alterable flash memory, and the state-of-art wear-leveling designs cannot resolve this problem. For tackling the problem, this study presents a duo-phase garbage collection scheme considering the page-level wear-leveling issue. The duo-phase mechanism simultaneously cares about page- and block-level wear-leveling issues. On the page-level wear-leveling problem, the duo-phase scheme identifies hot flash pages via the few bits and softly restricts the hot flash page to store hot data without sacrificing storage capacity. On the other hand, our proposed mechanism also figures out the solution to minimize the number of copied live pages for the block-level wear-leveling issue. According to the experimental results, our duo-phase scheme can prolong the lifespan of the bit-alterable flash memory by 1.5 to 1.9 times, compared with the state-of-art garbage collection mechanisms.

Abstract in Chinese iii
Abstract in English iv
Acknowledgements v
Table of Contents vi
List of Tables vii
List of Figures viii
Chapter 1 Introduction 1
Chapter 2 Background and Motivation 5
2.1 Bit-alterable NAND Flash Memory 5
2.2 Related Works 7
2.3 Motivation 9
Chapter 3 Duo-phase Garbage Collection Scheme 12
3.1 System Overview 12
3.2 The bit-count regulator 14
3.3 Hot-page Monitor 16
3.4 Data Placement Strategy 18
3.5 Duo-phase Garbage Collector 20
3.5.1 Performance-oriented Victim Selection 21
3.5.2 Inner-block Wear-leveling Strategy 23
3.6 Operations of Duo-phase Garbage Collection 24
3.7 Memory Footprint Analysis 27
Chapter 4 Performance Evaluation 29
4.1 Experimental Set-up 29
4.2 Performance Results 30
4.2.1 Endurance 30
4.3 Advanced Analysis 37
Chapter 5 Concluding Remarks 41
References 42

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