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研究生:徐尚輝
研究生(外文):Shang-Hui Hsu
論文名稱:操作於近臨界電壓之優於最差情況設計與分析
論文名稱(外文):Analysis and Design of Better-Than-Worst-Case Near Threshold Computing
指導教授:王進賢
指導教授(外文):Jinn-Shyan Wang
口試委員:林泰吉、葉經緯、黃俊銘、王進賢
口試委員(外文):LIN, TAY-JYI、YEH, CHING-WEI、HUANG, CHUN-MING、WANG, JINN-SHYAN
口試日期:2021-08-20
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2021
畢業學年度:109
語文別:中文
論文頁數:76
中文關鍵詞:優於最差情況設計抗變異技術近臨界電壓局部變異局部加速最差情況設計效能追求之優於最差情況設計
外文關鍵詞:Better-Than-Worst-Case designVariation resilientNear-thresholdLocal variationWorst-Case-DesignPerformance-driven BTWC
相關次數:
  • 被引用被引用:2
  • 點閱點閱:197
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章 傳統的抗變異技術 3
2.1 製程變異 3
2.2 先前抗變異技術 4
2.2.1 Tradition Latch-Based Design 7
2.3.2 Time Borrow and Local Boost 8
2.3 BTWC設計考量與手法 10
2.3.1 Razor-based BTWC 10
2.3.1 Skewed-clock pipelined 12
2.3.2 EFFORT 12
2.4 Performance-driven BTWC 13
第三章 The Proposed Design Performance-Driven BTWC 15
3.1 Near Threshold Computing & Super Threshold Computing 15
3.2 Performace-Driven BTWC 16
3.2.1 PD-BTWC Concepts and behaviors 16
3.2.2 PD-BTWC Design Flow 18
3.2.3 Latch Insertion Methodology 22
3.2.4 Second Stage & Power Gate Design Consideration 25
3.3 BTWC 定性分析 25
第四章 Analysis of Performance-Driven BTWC 27
4.1挑選載具 27
4.2時序分析 27
4.2.1 Accmulator & Power Gate Consideration 28
4.2.2 Replica Control Circuits Consideration 32
4.2.3 Replica with Monte–Carlo Consideration 37
4.2.4 PD-BTWC Post-Layout Simulation Result 41
4.3 Skewed-clock Pipelined 44
4.4 Razor-based BTWC 46
4.4.1 Razor-based BTWC post-layout simulation 48
第五章 BTWC comparison 50
5.1 WCD & BTWC with power gate 50
5.1.1 WCD MAC with power gate 50
5.1.2 PD-BTWC MAC with power gate 52
5.1.3 two stage multiplier with PD-BTWC 55
5.2 BTWC comparison 57
第六章 結論 59
6.1 結論 59
6.2 未來研究方向 59
參考文獻 61

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[8]J. Zhou et al., “ HEPP: A new in-situ timing-error prediction and prevention technique for variation-tolerant ultra-low-voltage designs ”, Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 129-132, Nov. 2013.
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