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研究生:張晏菱
研究生(外文):Yen-Ling Chang
論文名稱:具雙層鉿基鐵電材料的鐵電鰭式電晶體及其在記憶體應用之模擬研究
論文名稱(外文):A Simulation Study of Ferroelectric FinFET with Double-Layer Hf-based Ferroelectric materials and Memory Application
指導教授:張書通
指導教授(外文):Shu-Tong Chang
口試委員:唐英瓚李玟頡
口試委員(外文):Ying-Tsang TangWen-Jay Lee
口試日期:2021-06-11
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2021
畢業學年度:109
語文別:中文
論文頁數:49
中文關鍵詞:鉿基鐵電材料二氧化鉿鋯鐵電電晶體記憶視窗鐵電鰭式場效電晶體新興記憶體
外文關鍵詞:Hafnium-based ferroelectric materialHafnium zirconium oxide (HZO)Ferroelectric FETMemory windowFerroelectric FinFET(Fe-FinFET)Emerging memory
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隨著資訊時代的來臨,我們需要透過記憶體來儲存大量的資料,目前市場上記憶體主要以電荷儲存式為主。但這些記憶體都會面臨到微縮物理極限的問題,因此研究可微縮的記憶體變得相當重要。新興記憶體中的磁阻式記憶體、相變化式記憶體和電阻式記憶體分別具有材料製程方式複雜、操作功率消耗大、操作穩定度較差等問題。本次研究重點在具鉿基鐵電材料之1T鐵電電晶體,並可應用在鐵電記憶體中,該記憶體是採用極性轉換的方式儲存資料,有著與現行CMOS製程匹配,低功率消耗、操作穩定高等優勢,可作為探索可微縮新興非揮發性記憶體的重要主題。
本論文使用Sentaurus TCAD 的 Preisach模型來模擬鐵電電晶體,元件尺寸是根據IRDS 2020規範下3奈米與5奈米技術節點的鰭式場效電晶體,並在原有閘極加上二氧化鉿鋯鐵電層。我們提出具雙層鉿基鐵電鰭式場效電晶體,並與傳統單鐵電層之鐵電鰭式場效電晶體來比較。
從模擬結果顯示,具雙鐵電層的鐵電電晶體會擁有較大的記憶視窗。然而,足夠大的記憶視窗對於新興鐵電記憶體的儲存保留與耐久性至關重要,可做為定義0或者1的根據。同時分析3奈米5奈米技術節點下尺寸微縮對效能的影響,結果顯示與單鐵電層之鐵電鰭式場效電晶體相比,雙鐵電層之鐵電鰭式場效電晶體設計可以在記憶體特性上獲得不錯的效能提升。
With the advent of information age, memory devices are necessary for storing a large amount of data. The main type of the non-volatile memory (NVM) currently being widely circulated in the market is the charge storage flash memory. However, such memories face the physical limits of scaling that research on scalable memory becomes extremely important.
The emerging memory includes magneto resistive random access memory (MRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM), with the problems of complex material manufacturing process, high operating power consumption, and poor operation stability.
This research focuses on the one transistor (1T) Fe-FinFET with hafnium-based ferroelectric material, which can be applied to ferroelectric memory. The memory uses polarity switch to store data, which is compatible with CMOS process, shows the advantages of low power consumption and high Stable operation, and can be used as an important topic to explore emerging scalable NVM.
In this work, Preisach model of Sentaurus TCAD is used for simulating ferroelectric transistors. The transistor device structure is based on the 3nm/5nm technology node Fin-field-effect-Transistors (FinFET) under the IRDS 2020
specifications, and the hafnium zirconium oxide (HZO) ferroelectric layer is added to the original gate oxide. The proposed double-layer hafnium-based ferroelectric fin field
effect transistor (DL-Fe-FinFET) is compared with traditional single-layer fin field effect transistor (SL-Fe-FinFET).
第一章 緒論 1
1.1 記憶體介紹 1
1.1.1磁阻式隨機記憶體(MRAM) 2
1.1.2相變式隨機記憶體(PCRAM) 3
1.1.3電阻式隨機記憶體(RRAM) 4
1.1.4鐵電隨機記憶體(FeRAM) 5
1.1.5 新興鐵電記憶體(1T FeFET Memory) 6
1.2研究動機 8
第二章 鐵電材料特性與鐵電記憶體理論介紹 9
2.1鐵電材料特性 9
2.2鐵電電滯曲線 9
2.3 HfO2與Hf1-XZrXO2材料 10
2.4鐵電材料的負電容特性 12
2.4.1 鐵電材料的負電容理論 12
2.4.2 鐵電材料之負電容電壓放大理論 14
2.5 鐵電模型 16
第三章 文獻回顧 18
第四章 研究方法 22
第五章 研究結果 23
5.1單層鐵電鰭式場效電晶體(SL Fe-FinFET) 23
5.2雙層鐵電鰭式場效電晶體(DL Fe-FinFET) 27
5.3異質雙層鐵電鰭式場效電晶體(Hetero DL-FeFinFET) 31
5.4新型專利雙層鐵電鰭式場效電晶體 35
第六章 結論 44
第七章 未來工作 45
參考書目 46
附錄 48
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[3] Zahoor, F., Azni Zulkifli, T.Z. and Khanday, F.A. Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications. Nanoscale Res Lett 15,
[4] Huang, Q. 2013. TCAD simulation of Ferroelectric Field-Effect Transistor . PhD dissertation. Hunan: Xiangtan University, China
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[6] Takashima, D., "Overview of FeRAMs: Trends and perspectives", in 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding, (2011) pp. 1-6.
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[8] M.H. Lee, Y.-T. Wei, C. Liu, J.-J. Huang, M. Tang, Y.-L. Chueh, K.-Y. Chu, M.-J. Chen, H.-Y. Lee, Y.-S. Chen, L.-H. Lee and M.-J. Tsai, "Ferroelectricity of HfZrO2 in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors," IEEE Journal of the Electron Devices Society, vol.3, pp. 377-381, 2015. [9] S. Salahuddin and S. Datta, "Can the Subthreshold Swing in a Classical FET be Lowered Below 60 mV/decade?," IEDM Tech. Dig., pp. 693-696., 2008.
[10]劉謙, 使用鐵電負電容效應之低電壓超陡峭斜率電晶體模型及設計, 碩士論文, Ed. 台北: 國立台灣師範大學光電科技研究所, 2015.
[11 ] S. L. Miller and P. J. McWhorter, “Physics of the ferroelectric nonvolatile memory field effect transistor,” J. Appl. Phys., vol. 72, no. 12, pp. 5999–6010, 1992.
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[15] S. L. Miller, J. R. Schwank, R. D. Nasby, and M. S. Rodger,“Modeling of ferroelectric capacitor switching with asymmetry nonperiodic input signals and arbitrary initial conditions,” J. Appl. Phys., vol. 70, no. 5, pp. 2849–2860, 1991.
[16] Harshit Agarwa, Pragya Kushwaha, Yen-Kai Lin, Ming-Yen Kao, Yu-Hung Liao, Avirup Dasgupta, Sayeef Salahuddin, and Chenming Hu “ Proposal for Capacitance Matching in Negative Capacitance Field-Effect Transistors,”IEEE, Electron Device Letters, vol. 40, pp.464-466, 2019.

[17] Yu, H. S.,and Chui, C. O.(2015) “Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory. ” Unpublished doctoral dissertation University of California, Los Angeles.
[18] Chang, S.T, Lee,M.H, Tang,M., Chang,K.T, Lee,C.F, QIU,Y.Y, and Dai,Y.L,
“Semiconductor Device, ”R.O.C, I691078,2020
[19]Sentaurus Device User Guide Version N-2017.09, Synopsys, Mountain View,
CA, USA, 2017.
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