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研究生:李鴻宣
研究生(外文):Li, Hung-Hsuan
論文名稱:利用高度<111>優選方向奈米雙晶結構提升銅導線於扇出式晶圓級封裝的電遷移壽命
論文名稱(外文):Enhancement of electromigration lifetime of Cu redistribution layers in fan-out wafer level packaging by highly <111>-oriented nanotwinned structure
指導教授:陳智陳智引用關係
指導教授(外文):Chen, Chih
口試委員:杜經寧歐陽汎儀吳子嘉陳智
口試委員(外文):Tu, King-NingOuyang, Fan YiWu, Albert T.Chih, Chen
口試日期:2020-08-07
學位類別:碩士
校院名稱:國立交通大學
系所名稱:材料科學與工程學系所
學門:工程學門
學類:材料工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:109
語文別:中文
論文頁數:53
中文關鍵詞:電遷移扇出式晶圓級封裝奈米雙晶銅
外文關鍵詞:ElectromigrationFan-out Wafer Level PackagingNanotwinned Cu
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高密度扇出式晶圓級封裝(High density fan out wafer level packaging, HDFOWLP)工藝被認為是延續摩爾定律(Moore’s law)的關鍵技術,透過此封裝技術,可將邏輯晶片與高頻寬記憶體(High bandwidth memory, HBM)異質性地整合在一個封裝元件之中。隨著銅導線尺寸不斷地微縮,未來負責橋接邏輯晶片與高頻寬記憶體的導線將會承受高達107 A/cm2之電流密度,將會引發銅導線再分佈層(Redistribution layers, RDLs)如電遷移(Electromigration)破壞之可靠度議題。
於本研究中,我們設計出2μm與10μm線寬之導線結構,並使用直流電電鍍製備具高度<111>優選方向之奈米雙晶銅導線,再以聚醯亞胺(Poly-imide, PI)作為介電材料包覆導線完成表面鈍化,於大氣環境中之180℃加熱環境下,通以106 A/cm2之電流密度大小進行電遷移測試實驗。根據實驗結果,經過適當地熱處理之奈米雙晶銅導線的平均失效時間(Mean-time-to-failure, MTTF)最高可達一般銅導線的4倍。利用奈米雙晶銅具有低氧化速率與高度抗電遷移能力的特性,可以提升銅導線於扇出式晶圓級封裝的可靠度。除此之外,因為其可利用簡易的直流電電鍍法製備而成,與現今之半導體製程相匹配,未來具有量產製造之潛能。
Recently, high density fan-out wafer level packaging (FOWLP) has been recognized as a promising technique to extend the Moore’s law. By utilizing this technology, logic chips and high bandwidth memory(HBM) could be integrated heterogeneously into a packaging. As the Cu trace keeps shrinking, the interconnects between logic chips and HBM will be stressed by huge current density, for example, 107 A/cm2. Such a high current density will cause reliability issue such as electromigration(EM) in the Cu redistribution layers(RDLs).
In this study, we design the 2μm and 10μm width Cu RDLs protected by poly-imide, and electroplate highly <111>-orientated nanotwinned Cu RDLs by DC waveforms. We further stress the samples with electric current density at 106 A/cm2 under an ambient of 180℃. According to the experimental results, the mean-time-to-failure(MTTF) of nanotwinned Cu RDLs which undergoes proper annealing process can be increased to 4 times that of regular Cu RDLs. Due to the slower oxidation rate and high EM-resist characteristics, nanotwinned Cu could enhance the EM reliability of RDLs in FOWLP. In addition, this technology is highly compatible to the semiconductor process due to its simple fabrication method, which has the potential for the mass production in the future.
摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1-1 電子封裝技術簡介 1
1-2 三維積體電路 3
1-3 研究動機 5
第二章 文獻回顧 7
2-1 電遷移理論 7
2-2反向應力與關鍵乘積 10
2-3 焦耳熱效應 13
2-4 奈米雙晶銅 15
第三章 實驗方法 18
3-1 研究方法與試片設計 18
3-1.1 電遷移試片製備流程 18
3-1.2 試片製備參數 20
3-2 測試條件與方法 22
3-2.1 通電實驗設置 22
3-2.2 電阻溫度係數校正 22
3-3 分析工具與方法 23
第四章 結果與討論 24
4-1 試片結構確認 24
4-2 電阻溫度係數校正導線之實際溫度 30
4-3 電遷移測試 31
4-3.1 電遷移於10μm線寬銅導線試驗 31
4-3.2 電遷移於2μm線寬銅導線試驗 45
第五章 結論 50
參考文獻 51
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