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研究生:蔡宗函
研究生(外文):Tsai, Tzung-Han
論文名稱:應用於三維矽穿孔積體電路之主動式去耦電容電源雜訊抑制方法
論文名稱(外文):Power Noise Suppression Design Methodology using Active Decoupling Capacitors for TSV 3DIC
指導教授:陳宏明陳宏明引用關係黃柏蒼黃柏蒼引用關係
指導教授(外文):Chen, Hung-MingHuang, Po-Tsang
口試委員:劉建男林昌賜黃柏蒼陳宏明
口試委員(外文):Liu, Chien-NanLin, Chang-TzuHuang, Po-TsangChen, Hung-Ming
口試日期:2020-08-14
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:109
語文別:英文
論文頁數:69
中文關鍵詞:三維矽穿孔主動式去耦電容電源雜訊
外文關鍵詞:TSV 3DICActive Decoupling CapacitorPower Noise
相關次數:
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  • 下載下載:19
  • 收藏至我的研究室書目清單書目收藏:0
三維積體電路整合提升了系統整體的速度、能源效益及系統微小化,然而功耗密度也跟著增加,進而增加了電源雜訊及影響電源完整性。在本篇論文中,我們提出了主動式去耦電容電源雜訊抑制方法,有效地解決電源雜訊,進而改善三維積體電路中電源完整性。為了了解三維積體電路的電源供應問題,我們建立了三維矽穿孔供電網路模型,該模型可用於組合出所需的三維積體供電網路。並發現供電網路的阻抗在頻譜中產生了4個峰值,分別在低頻區域,中頻區域,高頻區域和超高頻區域。最大的電壓雜訊發生在高頻區域和超高頻區域。因此我們提出了一種功率傳輸網絡,在中介板和晶片上的供電網路中加入主動式開關去耦電容,以有效降低電壓雜訊。我們在系統單晶片中使用ASAP 7nm預測模型實現了所提出的主動式開關去耦電容。中介板上的主動式開關去耦電容用於進行全域電壓調節。它將中介板的阻抗降低了約50%。晶片上主動式開關去耦電容用於抑制區域供電網路的電壓雜訊和直流壓降。與被動式去耦電容相比,電壓雜訊和直流壓降的幅度分別減少了約31%和55%。主動電路的佈局面積約為4微米乘10微米,在單位電源網格中的面積僅佔0.4%。
TSV 3D integration can provide enormous advantages in improving system performance and energy efficiency. However, the increasing power density would lead to a large simultaneous switching noise and IR drop potentially. In this thesis, a power noise suppression design methodology is proposed using distributed fully-integrated LDO and active decoupling capacitors (DECAP) for TSV 3DICs. For analyzing the noise spectrum in TSV 3D integration, a TSV 3D IC PDN model is established. The largest voltage noise occurs at the high-frequency region and ultrahigh frequency region. Thus, we propose a power delivery network using active switched on-interposer and on-chip to reduce the voltage noise efficiently. Active on-interposer switched DECAPs are used for global voltage regulation that reduces the interposer impedance by almost 50%. Accordingly, active on-chip switched DECAPs are used to suppress voltage noise and IR drop at the local power network. The serious voltage drop of voltage noise and IR drop is reduced by about 31% and 55% compared with passive decoupling capacitor. The layout area of active circuit is about 4μm x 10μm, and the area overhead is only 0.4% in a grid.
Chapter 1 Introduction..................................1

1-1 Motivation..........................................1
1-2 Organization and Contribution.......................3

Chapter 2 Overview of Decoupling Capacitor & Power
Delivery Network..............................5

2-1 Power Delivery Network...........................5
2-2 PDN Impedance....................................6
2-3 Power Supply Noise...............................7
2-4 Decoupling Capacitor.............................7
2-4-1 Passive Decoupling Capacitor.....................8
2-4-2 Active Decoupling Capacitor.....................10
2-5 Conclusion......................................13

Chapter 3 Power Distribution Network in TSV 3D IC with
Active Decoupling Capacitor Circuits &
Distributed LDOs.............................14

3-1 Modeling and Analysis of PDN Impedance in TSV 3D IC Integration.............................................15
3-2 Analysis of Simultaneously Switching Noise.........21
3-2-1 Generate Current Profile........................22
3-2-2 Spectrum of Noise...............................23
3-3 Proposed PDN Architecture with Active Decoupling
Capacitor Circuits & Distributed Digital LDOs......26
3-4 Adding Distributed Digital LDO Regulator Model in
Power Delivery Network.............................27
3-4-1 Distributed Digital LDO Placement in 3D
PDN.............................................28
3-4-2 Synthesizable Distributed All-Digital
LDO.............................................29
3-4-3 Distributed Digital LDO Model...................31

Chapter 4 Active On-interposer Switched DeCAPs for Global
Voltage Regulation...........................33
4-1 Switched Decoupling Capacitor......................34
4-2 Low Pass Filter....................................35
4-3 Latch-based Comparator.............................35
4-4 Simulation Result..................................37

Chapter 5 Active On-Chip Switched DECAPs for Local
Voltage Regulation...........................41

5-1 Active Switched Decoupling Capacitor...............42
5-2 Waveform Synthesizer...............................44
5-3 Look-up Table for Mode Control.....................46
5-4 Level Shifter......................................48
5-5 Active Decoupling Capacitance......................49
5-6 Layout of Active On-Chip DECAPs....................50
5-7 Noise Suppression with Different Current Load......52
5-8 Case Study: 2D/3D Multi-Core SoCs..................55
5-9 Simulation Results.................................59

Chapter 6 Conclusions and Future Work..................65

6-1 Conclusion.........................................65
6-2 Future Work........................................65

Bibliography...........................................67
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