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研究生:林婕瑜
研究生(外文):Lin, Chieh-Yu
論文名稱:應用於5G NR之可重組LDPC編解碼器設計
論文名稱(外文):Implementation of Reconfigurable LDPC Codec for 5G NR Applications
指導教授:張錫嘉
指導教授(外文):Chang, Hsie-Chia
口試委員:陳燦文李鎮宜許騰尹張錫嘉
口試委員(外文):Chen, Tsan-WenLee, Chen-YiHsu, Terng-YinChang, Hsie-Chia
口試日期:2020-09-09
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:109
語文別:英文
論文頁數:69
中文關鍵詞:錯誤更正碼低密度奇偶校驗碼第五代行動通訊
外文關鍵詞:LDPC5GNRHardware ImplementationCodec
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5G NR作為新一代的行動通訊規格,除了以往常見的通訊及網路應用外,增加了更多的使用場景,而數據通道(data channel)的錯誤更正碼也從渦輪碼(turbo codes)改成採用低密度奇偶檢查碼(LDPC codes)。5G NR LDPC 碼更以新穎的結構設計,以滿足高吞吐量、低延遲以及高信賴度等性能要求。
本論文提出了適用於5G NR 的可重組LDPC 編解碼器,此可重組編解碼器支援5G NR LDPC 中的所有提升大小(lifting sizes)、基本圖形(base graphs)以及碼率(code rates),意即其可適用於102 種不同的奇偶檢查矩陣。本研究實現了針對5G NR LDPC 碼的可重組編碼器,該編碼器利用5G NR 中奇偶校驗矩陣的獨特結構,在不降低吞吐量的情況下降低編碼複雜度。透過正規化最小和演算法搭配基於列的分層調度(row-based layered scheduling),可在維持相近性能的情況下,減少所需的
解碼迭代次數。另外,經由本研究提出的流水線過程最佳化技術,包括指令級重新排序(instruction-level reordering) 以及數據級重新調度(data-level rescheduling),可解決解碼過程中遇到的數據依賴風險(data dependency hazard),從而在不增加成本的情況下顯著提高吞吐量。
以Xilinx VCU1525 FPGA 進行評估,此解碼器在111 MHz 的時鐘頻率下實現了0.67 Gbps 的吞吐量。透過TSMC 28nm CMOS 製程實作後,可以556 MHz 的時鐘頻率達到3.22 Gbps 的吞吐量,而核心面積為1.97 mm2。
As a new generation of mobile communication standards, fifth-generation new radio (5G NR) is desired for multiple usage scenarios besides the regular communication and network applications in previous standards. Low-density parity-check (LDPC) codes replace turbo codes, become the error correction code employed in 5G NR standard for the data channel. 5G NR LDPC codes are constructed with a novel structure to meet the broad performance demands, such as high throughput, low latency, and high reliability.
This thesis presents a reconfigurable LDPC codec implementation for 5G NR. The proposed reconfigurable LDPC decoder supports all lifting sizes, base graphs, and multiple code rates (i.e., adapting to 102 combinations of QC-LDPC matrices). This research implements a reconfigurable encoder that exploits the unique code structure in 5G NR LDPC to reduce the hardware complexity without degrading the throughput. A row-based layered scheduling normalized Min-Sum algorithm is employed to
reduce iterations while maintaining decoding performance. To further reduce the data dependency hazard in the decoding pipeline process, the proposed optimization approaches, including instruction-level reordering and data-level rescheduling, enhance the throughput significantly without the severe cost.
Evaluated in Xilinx VCU1525 FPGA, the proposed decoder achieves 0.67 Gbps throughput at a clock rate 111 MHz. After implementation in TSMC 28nm CMOS process, the proposed LDPC decoder can achieve 3.22 Gbps throughput at a clock rate 556 MHz with the core area 1.97 mm2.
1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
2 Low Density Parity Check Codes 4
2.1 Introduction to LDPC codes 4
2.2 Generic Encoding Methodologies 5
2.2.1 Encoder Using Gaussian Elimination 6
2.2.2 Encoder Using RU Method 6
2.3 Decoding Algorithms 8
2.3.1 Standard Belief Propagation (BP) Algorithm 8
2.3.2 Normalized Min-Sum (NMS) Algorithm 11
2.3.3 Row-Based Layered Scheduling Algorithm 11
3 Characteristics of 5G NR LDPC Codes 14
3.1 Introduction to 5G NR LDPC Codes 14
3.2 General Procedures 15
3.3 Structured QC-LDPC Code in 5G 17
4 Encoding Scheme 20
4.1 Efficient Encoding Methodology for 5G NR LDPC Codes 21
4.2 Reconfigurable Encoder for Multiple Lifting Sizes and Base Graphs 24
4.2.1 Implementation Results 26
5 Decoding Scheduling and Optimization 27
5.1 Decoding Scheduling Comparison and Selection 27
5.1.1 Implementation Challenge 28
5.2 Proposed Optimization Approaches 30
5.2.1 Conventional Row-Based Layered NMS 31
5.2.2 Instruction-level Reordering 32
5.2.3 Data-level Rescheduling 34
5.2.4 ROM Generating Procedure 39
5.3 Performance-related Parameters Decision 41
5.3.1 Channel Value Mapping and Quantization 41
5.3.2 Decoder Quantization 42
6 Hardware Architecture of Proposed LDPC Decoder 43
6.1 Decoder Architecture Overview 43
6.1.1 Pipeline Architecture 45
6.1.2 Storage Units 46
6.2 Variable Node Unit (VNU) 51
6.2.1 C2V Recovery 51
6.2.2 Lpost Updating 52
6.2.3 V2C Updating 53
6.3 Check Node Unit (CNU) 54
6.3.1 Accumulated Sorter and Sign Operation 55
6.4 Early Termination 56
6.4.1 Syndrome Check 56
7 Implementation Results of LDPC Decoder 57
7.1 ASIC Implementation Results 57
7.2 FPGA Implementation Results 61
8 Conclusion 63
8.1 Summary 63
8.2 Future Works 64
Reference 65
A Scaling Passing-Messages from Punctured Columns 68
[1] ETSI, “5G.” [Online]. Available: https://www.etsi.org/technologies/5g
[2] R. Gallager, “Low-density parity-check codes,” IRE Transactions on Information Theory, vol. 8, no. 1, pp. 21–28, 1962.
[3] D. J. C. MacKay and R. M. Neal, “Near shannon limit performance of low density parity check codes,” Electronics Letters, vol. 33, no. 6, pp. 457–458, 1997.
[4] D. J. C. MacKay, “Good error-correcting codes based on very sparse matrices,” IEEE Transactions on Information Theory, vol. 45, no. 2, pp. 399–431, 1999.
[5] NR; Multiplexing and channel coding, TS 38.212 Release 16, 3GPP, 2020.
[6] R. C. Bose and D. K. Ray-Chaudhuri, “On a class of error correcting binary group codes,” Information and control, vol. 3, no. 1, pp. 68–79, 1960.
[7] A. Hocquenghem, “Codes correcteurs d’erreurs,” Chiffres, vol. 2, no. 147-156, pp. 8–5, 1959.
[8] S. Benedetto and G. Montorsi, “Role of recursive convolutional codes in turbo codes,” Electronics Letters, vol. 31, no. 11, pp. 858–859, 1995.
[9] T. J. Richardson and R. L. Urbanke, “Efficient encoding of low-density paritycheck codes,” IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 638–656, 2001.
[10] J. Zhu, Y. Y. Tai, and X. Chen, “Universal and reconfigurable QC-LDPC encoder,” U.S. Patent 9 236 886 B1, 2016.
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