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研究生:徐立恩
研究生(外文):Hsu, Li-En
論文名稱:考慮時序優化之邏輯閘複製應用於多晶片FPGA
論文名稱(外文):Timing Driven Logic Replication on Multi-Die FPGAs
指導教授:陳宏明陳宏明引用關係
指導教授(外文):Chen, Hung-Ming
口試委員:陳宏明麥偉基劉時穎
口試委員(外文):Chen, Hung-MingMak, Wai-KeiLiu, Shih-Ying.
口試日期:2020-09-29
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:109
語文別:英文
論文頁數:32
中文關鍵詞:時序優化邏輯閘複製
外文關鍵詞:FPGALogic replicationmulti-dieTiming-Driven
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  • 收藏至我的研究室書目清單書目收藏:0
高性能多晶片FPGA近年來已開始商業化。 在整個設計過程的分群步驟之後,採用邏輯複製能夠減少時序關鍵路徑長。 在本篇論文中,我們提出了時序驅動邏輯複製方法。
它為關鍵路徑優化提出了兩個增強功能並且同時考慮到邏輯閘的數量容量限制和晶片之間連結線的數量限制。 首先,它使用一種新策略來防止其他非關鍵路徑中的時序下降。其次,為了在達成時序優化的同時使用最少數量的複製邏輯閘,我們將優化問題表述為最小覆蓋問題。實驗結果顯示,我們的方法能夠實現優異的性能。
High performance multi-die FPGAs have become commercially available in recent years. After the partitioning step of the design process, logic replication is adopted because of its great potential to reduce timing critical paths. In this work, the Timing-Driven Logic Replication method is proposed. Considering the logic capacity and the constraint of connection between dies, it proposes two enhancements for critical path optimization. First, it uses a new strategy to prevent timing degradation in other non-critical paths. Second, to achieve the optimization with minimum resources, it formulates the optimization problem as a minimum cover problem. In the experiment result, there are three approachs shown to be applied to solve this optimization problem. The results show that our method is capable of achieving good performance, which reaches 75\% and 18\% delay reduction than other two methods, also having 82\% and 33\% less resource usage.
Chapter 1 Introduction - 1
1.1 Compilation Flow for Multi-Die FPGA System - 1
1.2 Motivation - 4
1.3 Related Works - 7
1.4 Our Contributions - 7
1.5 Organization - 9
Chapter 2 Preliminary - 10
2.1 The Behavior of Logic Replication - 10
2.2 Terminologies - 10
2.3 Problem Formulation - 13
Chapter 3 Timing-Driven Logic Replication - 14
3.1 Overview - 14
3.2 Analysis on Replicating Sequential Logic - 14
3.3 Analysis on replicating combinational logic - 16
3.4 Replicate Sequential Logic via Greedy Approach - 17
3.5 Model Combinational Logic Replication as Min-Cover Problem - 19
3.5.1 Turning Point definition - 19
3.5.2 Minimum cover formulation - 21
3.6 Incrementally update the critical paths - 24
Chapter 4 Experimental Results - 25
Chapter 5 Conclusion - 30
References - 31
[1] ISPD 2016 : Routability-Driven FPGA Placement Contest. http://www.ispd.cc/
contests/16/ispd2016_contest.html.
[2] Xilinx. https://www.xilinx.com/support.html.
[3] Giancarlo Beraudo. A path based algorithm for timing driven logic replication in
FPGA. PhD thesis, Master’s thesis, University of Illinois at Chicago, 2002.
[4] Shih-Chun Chen, Richard Sun, and Yao-Wen Chang. Simultaneous partitioning and
signals grouping for time-division multiplexing in 2.5 d fpga-based systems. In 2018
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages
1–7. IEEE, 2018.
[5] Shounak Dhar, Mahesh A Iyer, Saurabh Adya, Love Singhal, Nikolay Rubanov, and
David Z Pan. An effective timing-driven detailed placement algorithm for fpgas. In
Proceedings of the 2017 ACM on International Symposium on Physical Design, pages
151–157, 2017.
[6] Charles M Fiduccia and Robert M Mattheyses. A linear-time heuristic for improving
network partitions. In 19th design automation conference, pages 175–181. IEEE,
1982.
[7] El Gamal et al. Optimal replication for min-cut partitioning. In 1992 IEEE/ACM
International Conference on Computer-Aided Design, pages 432–435. IEEE, 1992.
[8] William N.N. Hung and Richard Sun. Challenges in large fpga-based logic emulation
systems. In Proceedings of the International Symposium on Physical Design, ISPD
’18, pages 26–33, New York, NY, USA, 2018. ACM.
[9] L James Hwang and Abbas El Gamal. Min-cut replication in partitioned networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
14(1):96–106, 1995.
[10] G. Karypis and V. Kumar. Multilevel k-way hypergraph partitioning. In Proceedings
Design Automation Conference, pages 343–348, June 1999.
[11] George Karypis, Rajat Aggarwal, Vipin Kumar, and Shashi Shekhar. Multilevel
hypergraph partitioning: applications in vlsi domain. IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, 7(1):69–79, 1999.
[12] Sin-Hong Liou, Sean Liu, Richard Sun, and Hung-Ming Chen. Timing driven partition for multi-fpga systems with tdm awareness. In Proceedings of the 2020 International Symposium on Physical Design, pages 111–118, 2020.
[13] Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, and TC Hu. A replication cut for
two-way partitioning. IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 14(5):623–630, 1995.
[14] Wai-Kei Mak. Min-cut partitioning with functional replication for technologymapped circuits using minimum area overhead. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 21(4):491–497, 2002
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