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研究生:傅裕文
研究生(外文):Fu, Yu-Wen
論文名稱:電阻式記憶體中循環操作電壓條件之影響與讀取干擾錯誤時間劣化之研究
論文名稱(外文):Dependence of Endurance Characteristic on SET/RESET Operation Voltage Condition and Modeling of Read-Disturb Failure Time in RRAM
指導教授:汪大暉
指導教授(外文):Wang, Tahui
口試委員:古紹泓李岱螢譚至善汪大暉
口試委員(外文):Ku, Shau-HongLee, Dai-YingTan, Chih-ShanWang, Tahui
口試日期:2020-11-24
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2020
畢業學年度:109
語文別:英文
論文頁數:38
中文關鍵詞:電阻式記憶體耐受性循環操作應力讀取干擾裂化缺陷產生
外文關鍵詞:RRAMEndurance characteristiccycling stressread-disturbtrap generation
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本篇論文吾人探討氧化鎢電阻式記憶體中,不同操作電壓條件下對耐受性特性之影響及讀取干擾錯誤時間之模型。寫入/抹除之電流過衝現象會使氧化物陷阱加速產生進而造成耐受性劣化提早發生,吾人發現減緩電流過衝現象可抑制氧化物陷阱之產生速度,進一步改善耐受性劣化。元件於低阻值態下的讀取干擾錯誤時間隨著寫入/抹除的循環操作呈現翻轉特性,因寫入/抹除的循環操作生成的缺陷形成導電路徑,導致低阻態下的讀取干擾錯誤時間隨著寫入/抹除的循環次數增加而延長,其中此翻轉特性之轉折點與耐受性劣化有關。此外,基於氧化層崩潰模型,本篇論文對高阻值態下的讀取干擾錯誤時間模型中之低阻值態電流與導電燈絲的橫切面面積進行修正,其修正結果與實驗數據吻合。
In this thesis, the endurance characteristic on SET/RESET operation voltage condition and read-disturb failure in a tungsten oxide resistive random access memory are investigated. We found that the current overshoot effect in SET/RESET cycling stress induced trap creation would deteriorate the endurance failure. The current overshoot effect is minimized to suppress the trap generation and further improve the endurance characteristics. A turn-around feature of LRS disturb failure time is observed as cycle number increases. SET/RESET cycling stress-generated traps forming the percolation path results in the increase of LRS disturb failure time. However, the turning point of this feature is correlated with endurance failure. Regarding HRS disturb failure time model, the previous model is not accurate due to the wrong area dependence of current level in LRS. Thus, based on the oxide breakdown model, the area dependence of current level in LRS is modified and our model is in good agreement with experiment results.
Contents
Chinese Abstract i
English Abstract ii
Acknowledgement iii
Contents iv
Figure Captions v
Chapter 1 Introduction 1
Chapter 2 Cycling Induced LRS Disturb Failure Time Degradation 8
2.1 Introduction 8
2.2 Device Structure and Measurement Setup 8
2.3 Endurance Characteristic on SET/RESET Operation Voltage Condition 9
2.4 Turn-Around Behavior of LRS Disturb Failure Time 10
Chapter 3 Modeling of HRS Disturb Failure Time 23
3.1 Introduction 23
3.2 Window Effect on HRS Disturb Failure Time 23
3.3 Modification of HRS Disturb Failure Time Model 24
Chapter 4 Conclusion 32
Reference 33
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