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研究生:張哲嘉
研究生(外文):Chang, Che-Chia
論文名稱:原子層氣相沉積之雙層非阻絲電阻式記憶體於高密度交錯式陣列應用之探討
論文名稱(外文):Exploring ALD Bilayer Non-Filamentary RRAM for Ultra-High Density Crossbar Array Applications
指導教授:侯拓宏劉柏村劉柏村引用關係
指導教授(外文):Hou, Tuo-HungLiu, Po-Tsung
口試委員:金雅琴巫勇賢曾俊元林詩淳侯拓宏劉柏村
口試委員(外文):King, Ya-ChinWu, Yung-HsienTseng, Tseung-YuenLin, Shih-ChunHou, Tuo-HungLiu, Po-Tsung
口試日期:2021-1-06
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2021
畢業學年度:109
語文別:英文
論文頁數:104
中文關鍵詞:電阻式記憶體交錯式陣列仿生系統人工智慧陣列良率分析脈衝性神經網路非阻絲形態電組式記憶體ˇ
外文關鍵詞:RRAMCrossbar arrayNeuromorphic computingArtificial intelligenceArray yield analysisSpiking neuron networkNon-filamentary RRAM
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在現今大數據以及物聯網的時代之下,巨量資料的運算與儲存每年正指數性的劇增。於此同時,人工智慧的快速發展有效地加速了數據的分析能力,支撐了現今方便快速的科技社會。在這樣的時空背景之下,無論是在現行傳統馮 • 諾伊曼之電腦架構下能填補速度與容量缺口的高密度儲存級記憶體,亦或是發展跳脫於此架構下的新平台進行更有效率的人工智慧運算硬體,各種新世代的記憶體近十幾年來引起了學界與業界的高度關注,相關的各式應用也陸續被提出。
電阻式記憶體由於其簡單結構提供了元件微縮上的優勢,展現了超高密度陣列架構的實現可行性,並提供前述所言之應用潛力。以高密度三維結構的製程技術而言,原子層氣相沉積是不可或缺的薄膜沉積技術,提供在三維側壁結構下良好的薄膜覆蓋與均勻性。以元件的特性而言,傳統以阻絲形態為傳導機制的電阻式記憶體在上述前提之下出現了許多元件本身的挑戰。其線性的電阻與電壓的依存關係造成了高密度記憶體陣列中嚴重的漏電流問題,並且因製程的困難無法允許其在三維側壁結構的設計下串接額外的選擇性元件用以降低漏電流。再者,由於阻絲的連接與斷裂往往是一不連續且隨機的雙穩態變化,而在仿生人工智慧之硬體平台上往往需要類比形態阻值切換的元件技術。大範圍的元件與元件或者操作之間的變異性亦增加陣列操作的困難度。另一方面,各式非阻絲形態的電阻式記憶體近年來被許多團隊提出,因其均勻的電流傳導機制,非線性之電壓電流關係,漸進式的阻值切換,以及均勻的操作穩定性皆克服了前述阻絲形態電阻式記憶體所遭遇之困難。然而,相較於在操作機制上相當明朗的阻絲形態電阻式記憶體,非阻絲操作行為背後的機制一直受到廣泛的爭議。機制的不明確對於後續元件的優化與應用的發展造成許多阻礙。
本篇論文旨在針對非阻絲形態電阻式記憶體在元件機制、元件應用、陣列整合上的議題做各種探討與開發,展望於未來應用於儲存級記憶體與人工智慧上之高密度記憶體陣列結構。我們成功以原子層氣相沉積的技術發展出了以HfO2/TiO2雙層介電層結構為基礎的非阻絲形態電阻式記憶體,透過電性以及物性的分析確定了氧化層缺陷能階的形成是主導此非阻絲傳導機制的關鍵。電子在缺陷內的捕捉或釋放改變了材料本身的特性,因而改變了整體結構的電流傳導。我們更發現氧空缺之帶電性能進一步形成氧空缺聚集或者斷裂的行為。透過製程條件的調變,我們可以在同一元件上操作脈衝時序依賴可塑性(STDP)及反脈衝時序依賴可塑性(anti-STPD)之仿生突觸行為。如此能完全符合最新一代人工智慧網路裡的監督式學習演算法之突觸特性。更進一步,我們提出了一可行之突觸陣列硬體平台,成功的對資料的分類進行高準確的運算。最後,在考量非理想的元件良率的情況下,我們定量的討論了元件因非理想效應崩潰之後對整體陣列上造成的干擾。元件的崩潰不但使得其非阻絲操作的非線性電壓電流關係消失,亦造成了元件本身大量的漏電,因此對陣列上其他正常的元件造成巨大的漏電流影響。透過分析主要的干擾模式並且簡化陣列的電路做等效模型的計算,我們提出了一規則化的方法快速且系統性地分析了元件良率對陣列良率的關係。我們發現即使只有少量的崩潰元件,亦將對陣列的良率造成嚴重的劣化,越大的陣列尺寸造成的影響將更劇烈,必需使用更多的陣列以彌補良率的損失,因而可能失去了與主流一電晶體一記憶體(1T1R)陣列結構相比的面積優勢。未來針對元件因崩潰帶來的影響,需要透過陣列參數的調整,或者是適當的陣列切割,亦或是備用陣列的安排,慎重考量並設計之。
With the arrival of the Big Data era and the continuous evolution of Internet-of-things (IoT), the enormous amount of data for processing and storage has surged exponentially every year. At the same time, the development of artificial intelligence (AI) has proliferated to improve the computing efficiency for data analysis. In recent years, emerging memories have aroused numerous attentions to realize high-density storage classed memory (SCM) and to develop a new computing platform beyond the current von-Neumann architecture for AI.
Due to the simple metal-insulator-metal (MIM) structure of resistive random access memory (RRAM), the superiority in device-scaling makes RRAM a feasible technology for realizing the ultimate high-density 3D vertical crossbar architecture for SCM and AI. From the aspect of fabricating ultimate 3D scaled array structures, atomic layer deposition (ALD) is the critical solution providing satisfactory film uniformity and conformity. Concerning the device characteristics, the conventional filamentary-based RRAM confronts several device-level challenges that impede its further development toward those high-density applications: (a) the linear voltage-to-current (I-V) relation in low resistance state (LRS) causes severe sneak current issues for the array integration. This is particularly problematic for the 3D vertical architecture since the selection device is not allowed to connect with RRAM for suppressing the leakage. (b) The bistable change of resistance states is not favorable to replicate the analog-like electronic synapse for the neuromorphic AI hardware platform. (c) Significant device-to-device and cycle-to-cycle variations are also critical concerns that deteriorate the write and read margins of the array. By contrary, RRAM with the non-filamentary conducting mechanism has been proposed by several groups. The non-filamentary based RRAM possesses non-linear I-V, gradual change of the resistance states, and uniform cycling stability. These merits overcome the difficulties that the filamentary devices face. However, the fundamental issue of non-filamentary RRAM is that the RS mechanism is still highly controversial, which largely obstructs the progress of optimizing the device characteristics toward developing relevant applications.
This thesis aims to give a thorough study of the non-filamentary RRAM through three aspects: the clarification of device mechanism, the feasible application for neuromorphic computing, and the integration concerns on the array yield. The purpose is to explore the full advantages and challenges of non-filamentary RRAM envisioning in future ultimate high-density memory architecture for SCM and neuromorphic applications. We began with the successful development of an ALD-grown HfO2/TiO2 based bilayer non-filamentary RRAM. The electronic effect of charge injection/extraction on the defect sites is confirmed to be the RS origin. This effect changes the material properties and the current transportation behavior. We further observed the oxygen vacancies (VO) clustering effect inside the metal-oxide, which is induced by the change of the VO charged states. Based on this specific device, we realized the analog synaptic activities of Hebbian spike-timing-dependent plasticity (STDP) and anti-STDP due to its dual-mode RS feature. This feature perfectly matches with the desired synaptic characteristics for the latest generation of the artificial neuron network model. A feasible hardware design was proposed and achieved sufficient accuracy for MNIST data classification. Finally, we discussed the influence of the non-ideal device yield issue due to cell breakdown (BD) on the 1R crossbar array. Although the non-linear I-V relation of the non-filamentary RRAM favors a selector-less 1R array design, the breakdown of the cell results in the vanish of the non-linear I-V feature and the significant cell-leakage. These leakages greatly influence the other normal cells in the array. We proposed a rule-based method to quantitatively calculate the relation between array yield (due to cell-to-cell interferences) and device yield (due to cell BD) by analyzing the primary interference modes and simplifying the circuit calculation. The results revealed that the array yield deteriorates severely, even with only a small amount of the BD cells. This influence is even more considerable when the array size increases. Therefore, a larger array doesn’t guarantee a higher storage capacity. More numbers of the arrays are required to compensate the yield loss for a given storage capability, and the area penalty can increase significantly. Whether the 1R crossbar array with the 4F2 minimum cell size can still be competitive with its advantage of a smaller array area than the mainstream 1T1R design remains questionable. The tuning of the device and array parameters, the density-optimized array partition for a specified device yield, and the redundant design for compensating array yield loss are a few potential directions to be investigated in the future.
摘 要 I
Abstract III
Acknowledgment VI
Contents VIII
Figure Captions XI
Table List XX
Chapter 1 1
1.1 Background 1
1.2 Resistive Random Access Memory (RRAM) 2
1.2.1 Basic Operation and the Filamentary Based RRAM 2
1.2.2 Non-Filamentary RRAM 6
1.3 Crossbar Array Architecture 10
1.3.1 2 Dimensional Stacked Crossbar Array 10
1.3.2 3 Dimensional Stacked Crossbar Array 13
1.4 Brain-Inspired Artificial Intelligence 16
1.4.1 Neuromorphic Computing 16
1.4.2 Spike-Time-Dependent Plasticity (STDP) 17
1.4.3 Spiking Neuron Network (SNN) 21
1.5 Motivation 22
1.6 Thesis Organization 23
Chapter 2 25
2.1 Introduction 25
2.2 Experimental Details 26
2.3 Analog Switching Characteristic 27
2.4 Mechanism Study 29
2.4.1 Area Dependent RS Relation 29
2.4.2 Different Stack-Combinations Experiment 30
2.4.3 Structural and Optical Analysis 31
2.4.4 VO Defect Investigation 32
2.4.5 Electronic Switching Model 34
2.5 Device Engineering 36
2.5.1 Effect of Al-Doping 36
2.5.2 Effect of the TE Reactiveness 38
2.5.3 Reliability Study via Physical Analysis 40
2.6 Summary 43
2.7 Acknowledgements 43
Chapter 3 44
3.1 Introduction 44
3.2 Experimental Details 46
3.3 Effect of in-situ NH3 Plasma 47
3.4 Dual-mode Switching Characteristic and the Mechanism Study 48
3.4.1 Dual-Mode Switching 48
3.4.2 Area-Dependent Resistance State 50
3.4.3 Experiment of Different Stacking Combinations 52
3.4.4 Activation Energy (Ea) 54
3.4.5 Conductive-Atomic Force Measurements (C-AFM) 55
3.4.6 Proposed Electronic Model 58
3.5 STDP and Anti-STDP Synaptic Behavior 60
3.6 ReSuMe SCNN Using Dual STDP Synapse 63
3.7 Summary 68
3.8 Acknowledgements 68
Chapter 4 69
4.1 Introduction 69
4.2 Ni/HfO2/Al:TiO2/TiN 1R Crossbar Array 70
4.2.1 Experimental Details 70
4.2.2 Array Characteristic 71
4.3 Interference Mode Analysis 72
4.3.1 Read Interference 73
4.3.2 Write Interference 80
4.4 Monte-Carlo Array Simulation and Result Discussion 82
4.5 Design Consideration for BD Interference 85
4.6 Summary 86
Chapter 5 88
5.1 Summary of Contribution 88
5.2 Future Recommendation 89
Reference 92
Vita 102
Publication List 103
[1] Z. Wang, F. Su, Y. Wang, Z. Li, X. Li, R. Yoshimura, et al., "A 130nm FeRAM-based parallel recovery nonvolatile SOC for normally-OFF operations with 3.9× faster running speed and 11× higher energy efficiency using fast power-on detection and nonvolatile radio controller," in Proc. Symp. VLSI Circuit (VLSI), 2017, pp. C336-C337.
[2] J. S. Yoon, A. Tewari, C. Shin, and S. Jeon, "Influence of High-Pressure Annealing on Memory Properties of Hf0.5Zr0.5O2 Based 1T-FeRAM," in IEEE Electron Device Lett., pp. 1076-1079, 2019.
[3] M.-H. Wu, M.-C. Hong, C.-C. Chang, P. Sahu, J.-H. Wei, H.-Y. Lee, et al., "Extremely Compact Integrate-and-Fire STT-MRAM Neuron: A Pathway toward All-Spin Artificial Deep Neural Network," in Proc. Symp. VLSI Technol. (VLSIT), 2019, pp. T34-T35.
[4] F.-X. Liang, P. Sahu, M.-H. Wu, J.-H. Wei, S.-S. Sheu, and T.-H. Hou, "Stochastic STT-MRAM Spiking Neuron Circuit," in International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2020, pp. 151-152.
[5] J.G. Alzate, U. Arslan, P. Bai, J. Brockman, Y.J. Chen, N. Das, et al., " 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications" in Proc. Int. Electron Devices Meeting (IEDM), 2019, pp. 2.4.1-2.4.4.
[6] T. Kim, H. Choi, M. Kim, J. Yi, D. Kim, S. Cho, et al., "High-performance, cost-effective 2z nm two-deck cross-point memory integrated by self-align scheme for 128 Gb SCM," n Proc. Int. Electron Devices Meeting (IEDM), 2018, pp. 37.1.1-37.1.4.
[7] O. Golonzka, U. Arslan, P. Bai, M. Bohr, O. Baykan, Y. Chang, et al., "Non-volatile RRAM embedded into 22FFL FinFET technology," in Proc. Symp. VLSI Technol. (VLSIT), 2019, pp. T230-T231.
[8] B. Hudec, C.-W. Hsu, I.-T. Wang, W.-L. Lai, C.-C. Chang, T. Wang, et al., "3D resistive RAM cell design for high-density storage class memory—a review," Sci. China Inf. Sci., vol. 59, 061403, 2016.
[9] C.-W. Hsu, I.-T. Wang, C.-L. Lo, M.-C. Chiang, W.-Y. Jang, C.-H. Lin, and T.-H. Hou, “Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory,” in Proc. Symp. VLSI Technol. (VLSIT), 2013, pp. T166–T167.
[10] C.-W. Hsu, Y.-F. Wang, C.-C. Wan, I.-T. Wang, C.-T. Chou, et al., “Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory,” Nanotechnology, vol. 25, 165202, 2014.
[11] C.-C. Chang, P.-C. Chen, B. Hudec, P.-T. Liu, and T.-H. Hou, "Interchangeable Hebbian and anti-Hebbian STDP applied to supervised learning in spiking neural network," in Proc. Int. Electron Devices Meeting (IEDM), 2018, pp. 15.5.1-15.5.4.
[12] K. Moon, S. Lim, J. Park, C. Sung, S. Oh, J. Woo, et al., "RRAM-based synapse devices for neuromorphic systems," Faraday Discuss., vol. 213, pp. 421-451, 2019.
[13] I.-T. Wang, C.-C. Chang, L.-W. Chiu, T. Chou, and T.-H. Hou, “3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications,” Nanotechnology, vol. 27, 365204, 2016.
[14] Y.-F. Wang, Y.-C. Lin, I.-T. Wang, T.-P. Lin, and T.-H. Hou, "Characterization and Modeling of Non-filamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device," Sci Rep, vol. 5, p. 10150, 2015.
[15] S. Lashkare, N. Panwar, P. Kumbhare, B. Das, and U. Ganguly, "PCMO-Based RRAM and NPN Bipolar Selector as Synapse for Energy Efficient STDP," IEEE Electron Device Lett., vol. 38, pp. 1212-1215, 2017.
[16] H.-Y. Chen, S. Brivio, C.-C. Chang, J. Frascaroli, T.-H. Hou, B. Hudec, et al., "Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication," J. Electroceramics, vol. 39, pp. 21-38, 2017.
[17] D. H. Kwon, K. M. Kim, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim, et al., "Atomic structure of conducting nanofilaments in TiO2 resistive switching memory," Nat Nanotechnol., vol. 5, pp. 148-53, 2010.
[18] R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects, and Challenges," Adv. Mater., vol. 21, pp. 2632-2663, 2009.
[19] X. Guo, C. Schindler, S. Menzel, and R. Waser, "Understanding the switching-off mechanism in Ag+ migration based resistively switching model systems," Appl. Phys. Lett., vol. 91, p. 133513, 2007.
[20] W. Chen, S. Tappertzhofen, H. J. Barnaby, and M. N. Kozicki, "SiO2 based conductive bridging random access memory," J. Electroceramics, vol. 39, pp. 109-131, 2017.
[21] H. S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, et al., "Metal–Oxide RRAM," Proc. IEEE, vol. 100, pp. 1951-1970, 2012.
[22] C. Y. Chen, L. Goux, A. Fantini, R. Degraeve, A. Redolfi, G. Groeseneken, et al., "Stack optimization of oxide-based RRAM for fast write speed (<1 μs) at low operating current (<10 μA)," Solid State Electron., vol. 125, pp. 198-203, 2016.
[23] R. Degraeve, A. Fantini, N. Raghavan, L. Goux, S. Clima, B. Govoreanu, et al., "Causes and consequences of the stochastic aspect of filamentary RRAM," Microelectron. Eng., vol. 147, pp. 171-175, 2015.
[24] G. Molas, G. Sassine, C. Nail, D. Alfaro Robayo, J.-F. Nodin, C. Cagli, et al., "(Invited) Resistive Memories (RRAM) Variability: Challenges and Solutions," ECS Transactions, vol. 86, pp. 35-47, 2018.
[25] Z. Swaidan, R. Kanj, J. El Hajj, E. Saad, and F. Kurdahi, "RRAM Endurance and Retention: Challenges, Opportunities and Implications on Reliable Design," in Proc. Int. Electron Devices Meeting (IEDM), 2019, pp. 402-405.
[26] P. Pouyan, E. Amat, S. Hamdioui, and A. Rubio, "RRAM variability and its mitigation schemes," in Proc. Int. Memory Workshop (IMW), 2016, pp. 141-146.
[27] T. Fujii, M. Kawasaki, A. Sawa, Y. Kawazoe, H. Akoh, and Y. Tokura, "Electrical properties and colossal electroresistance of heteroepitaxial SrRuO3∕SrTi1−xNbxO3 (0.0002≤x≤0.02) Schottky junctions," Phys. Rev. B, vol. 75, 2007.
[28] M. Hansen, M. Ziegler, L. Kolberg, R. Soni, S. Dirkmann, T. Mussenbrock, et al., "A double barrier memristive device," Sci Rep, vol. 5, p. 13753, 2015.
[29] B. Govoreanu, L. Di Piazza, J. Ma, T. Conard, A. Vanleenhove, A. Belmonte, et al., "Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability," in Proc. Int. Memory Workshop (IMW), 2016, pp. 1-2.
[30] K. Baek, S. Park, J. Park, Y. M. Kim, H. Hwang, and S. H. Oh, "In situ TEM observation on the interface-type resistive switching by electrochemical redox reactions at a TiN/PCMO interface," Nanoscale, vol. 9, pp. 582-593, Jan 5 2017.
[31] J. H. Yoon, S. J. Song, I.-H. Yoo, J. Y. Seok, K. J. Yoon, D. E. Kwon, et al., "Highly Uniform, Electroforming-Free, and Self-Rectifying Resistive Memory in the Pt/Ta2O5/HfO2-x/TiN Structure," Adv. Funct. Mater., vol. 24, pp. 5086-5095, 2014.
[32] K. M. Kim, B. J. Choi, M. H. Lee, G. H. Kim, S. J. Song, J. Y. Seok, et al., "A detailed understanding of the electronic bipolar resistance switching behavior in Pt/TiO2/Pt structure," Nanotechnology, vol. 22, p. 254010, 2011.
[33] K. M. Kim, J. Zhang, C. Graves, J. J. Yang, B. J. Choi, C. S. Hwang, et al., "Low-Power, Self-Rectifying, and Forming-Free Memristor with an Asymmetric Programing Voltage for a High-Density Crossbar Application," Nano Lett., vol. 16, pp. 6724-6732, 2016.
[34] X. L. Shao, L. W. Zhou, K. J. Yoon, H. Jiang, J. S. Zhao, K. L. Zhang, et al., "Electronic resistance switching in the Al/TiO(x)/Al structure for forming-free and area-scalable memory," Nanoscale, vol. 7, pp. 11063-74, 2015.
[35] J.-J. Huang, Y.-M. Tseng, W.-C. Luo, C.-W. Hsu, and T.-H. Hou, “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications,” in Proc. Int. Electron Devices Meeting (IEDM), 2011, pp. 733–736.
[36] C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, "Dependence of read margin on pull-up schemes in high-density one selector-one resistor (1S1R) crossbar array," IEEE Trans. Electron Device, vol. 60, no. 1, pp.420-426, 2013.
[37] A. Chen, "A comprehensive crossbar array model with solutions for line resistance and nonlinear device characteristics," IEEE Trans. Electron Device, vol. 60, no. 4, pp. 1318-1326, 2013.
[38] K. Sungho, Z. Jiantao, and W. D. Lu, "Crossbar RRAM Arrays: Selector Device Requirements During Write Operation," IEEE Trans. Electron Device, vol. 61, pp. 2820-2826, 2014.
[39] V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, et al., "Punchthrough-diode-based bipolar RRAM selector by Si epitaxy," IEEE Electron Device Lett., vol. 33, no. 10, pp. 1396-1398, 2012.
[40] J.-J. Huang, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, "Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode," Appl. Phys. Lett., vol. 96, p. 262901, 2010.
[41] M. J. Lee, Y. Park, B. S. Kang, S. E. Ahn, C. Lee, K. Kim, et al., "2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications," in Proc. Int. Electron Devices Meeting (IEDM), 2007, pp. 771-774.
[42] X. A. Tran, B. Gao, J. F. Kang, L. Wu, Z. R. Wang, Z. Fang, et al., "High performance unipolar AlOy/HfOx/Ni based RRAM compatible with Si diodes for 3D application," in Proc. Symp. VLSI Technol. (VLSIT), 2011, pp. 44-45.
[43] J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, "Bipolar nonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications," IEEE Electron Devices Lett., vol. 32, no. 10, pp. 1427-1429, 2011.
[44] S. H. Jo, T. Kumar, S. Narayanan, and H. Nazarian, "Cross-point resistive RAM based on field-assisted superlinear threshold selector," IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3477-3481, 2015.
[45] R. Midya, Z. Wang, J. Zhang, S. E. Savel'ev, C. Li, M. Rao, et al., "Anatomy of Ag/Hafnia-based selectors with 1010 nonlinearity," Adv. Mater., vol. 29, 1604457, 2017.
[46] Q. Hua, H. Wu, B. Gao, M. Zhao, Y. Li, X. Li, et al., "A threshold switching selector based on highly ordered Ag nanodots for X-point memory applications," Adv. Sci., vol. 6, 1900024, 2019.
[47] M. Lanza, "A Review on Resistive Switching in High-k Dielectrics: A Nanoscale Point of View Using Conductive Atomic Force Microscope," Mater. (Basel), vol. 7, pp. 2155-2182, 2014.
[48] S. E. Ahn, I. k. Yoo, Y. S. Joung, Y K. Cha, M. J. Lee, et al., "Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same," US Patent 7,602,042, 2009.
[49] J.-J. Huang, Y.-M. Tseng, W.-C. Luo, C.-W. Hsu, and T.-H. Hou, “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications,” in Proc. Int. Electron Devices Meeting (IEDM), 2011, pp. 733-736.
[50] B. J. Choi, J. Zhang, K. Norris, G. Gibson, K. M. Kim, W. Jackson, et al., "Trilayer Tunnel Selectors for Memristor Memory Cells," Adv Mater, vol. 28, pp. 356-62, 2016.
[51] J. Woo, W. Lee, S. Park, S. Kim, D. Lee, et al., "Multi-layer tunnel barrier (Ta2O5/TaOx/TiO2) engineering for bipolar RRAM selector applications," in Proc. Symp. VLSI Technol. (VLSIT), 2013, pp. T168-T169.
[52] W. Lee, J. Park, J. Shin, J. Woo, S. Kim, G. Choi, et al., "Varistor-type bidirectional switch (JMAX>107A/cm2, selectivity∼104) for 3D bipolar resistive memory arrays," in Proc. Symp. VLSI Technol. (VLSIT), 2012, pp. 37-38.
[53] R. S. Shenoy, G. W. Burr, K. Virwani, B. Jackson, A. Padilla, P. Narayanan, et al., "MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays," Semicond. Sci. Technol., vol. 29, p. 104005, 2014.
[54] G. W. Burr, K. Virwani, R. S. Shenoy, A. Padilla, M. BrightSky, E. A. Joseph, et al., "Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction (MIEC) at 100% yield," in Proc. Symp. VLSI Technol. (VLSIT), 2012, pp. 41-42.
[55] C. Sung, J. Song, D. Lee, S. Lim, M. Kwak, and H. Hwang, "Ultra-thin <10nm) Dual-oxide (Al2O3/TiO2) Hybrid Device (Memory/Selector) with Extremely Low Ioff <1nA) and Ireset <1nA) for 3D Storage Class Memory," in Proc. Symp. VLSI Technol. (VLSIT), 2019, pp. T62-T63.
[56] J. Song, J. Park, K. Moon, J. Woo, S. Lim, J. Yoo, et al., "Monolithic integration of AgTe/TiO2 based threshold switching device with TiN liner for steep slope field-effect transistors," in Proc. Int. Electron Devices Meeting (IEDM), 2016, pp. 25.3.1-25.3.4.
[57] N. S. Avasarala, G. L. Donadio, T. Witters, K. Opsomer, B. Govoreanu, A. Fantini, et al., "Half-threshold bias Ioff reduction down to nA range of thermally and electrically stable high-performance integrated OTS selector, obtained by Se enrichment and N-doping of thin GeSe layers," in Proc. Symp. VLSI Technol. (VLSIT), 2018, pp. 209-210.
[58] Q. Luo, J. Yu, X. Zhang, K.-H. Xue, J.-H. Yuan, Y. Cheng, et al., "Nb1-xO2 based Universal Selector with Ultra-high Endurance (>1012), high speed (10ns) and Excellent Vth Stability," in Proc. Symp. VLSI Technol. (VLSIT), 2019, pp. T236-T237.
[59] I. G. Baek, C. J. Park, H. Ju, D. J. Seong, H. S. Ahn, J. H. Kim, et al., "Realization of vertical resistive memory (VRRAM) using cost effective 3D process," in Proc. Int. Electron Devices Meeting (IEDM), 2011, pp. 31.8.1-31.8.4.
[60] K.-T. Park, J.-m. Han, D. Kim, S. Nam, K. Choi, M.-S. Kim, et al., "19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming," in IEEE Int. Solid-State Circuits Conference (ISSCC), 2014, pp. 334-335.
[61] N. Shibata, T. Kawabe, T. Shibuya, M. Sako, K. Yanagidaira, T. Hashimoto, et al., "A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology," IEEE J. Solid-State Circuits, vol. 55, pp. 178-188, 2020.
[62] Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, et al., "Design and optimization methodology for 3D RRAM arrays," in Proc. Int. Electron Devices Meeting (IEDM), 2013, pp. 25.7.1-25.7.4.
[63] Xu C, Niu D, Yu S, Xie Y. Modeling and design analysis of 3D vertical resistive memory—a low cost cross-point architecture. in Proc. of 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp. 825-830.
[64] S. Yu, H. Y. Chen, Y. Deng, B. Gao, Z. Jiang et al., “3D vertical RRAM-scaling limit analysis and demonstration of 3D array operation,” in Proc. Symp. VLSI Technol. (VLSIT), 2013, pp. 158-159.
[65] Y. Bai, H. Wu, R. Wu, Y. Zhang, N. Deng, Z. Yu, et al., "Study of multi-level characteristics for 3D vertical resistive switching memory," Sci Rep, vol. 4, p. 5780, 2014.
[66] Q. Luo, X. Xu, T. Gong, H. Lv, D. Dong, H. Ma, et al., "8-Layers 3D vertical RRAM with excellent scalability towards storage class memory applications," in Proc. Symp. VLSI Technol. (VLSIT), 2017, pp. 2.7.1-2.7.4.
[67] H. Y. Chen, S. Yu, B. Gao, P. Huang, J. Kang, and H. S. P. Wong, "HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector," in Proc. Symp. VLSI Technol. (VLSIT), 2012, pp. 20.7.1-20.7.4.
[68] S. Park, H. Kim, M. Choo, J. Noh, A. Sheri, S. Jung, K. Seo, J. Park, S. Kim, W. Lee, J. Shin, D. Lee, G. Choi, J. Woo, E. Cha, J. Jang, C. Park, M. Jeon, B. Lee, B. H. Lee, and H. Hwang, “RRAM-based synapse for neuromorphic system with pattern recognition function,” in Proc. Int. Electron Devices Meeting (IEDM), 2012, pp. 231-234.
[69] S. M. Dudek and M. F. Bear, "Homosynaptic long-term depression in area CA1 of hippocampus and effects of N-methyl-D-aspartate receptor blockade," Proc. Natl. Acad. Sci. U. S. A., vol. 89, pp. 4363-7, 1992.
[70] G.-q. Bi and M.-m. Poo, "Synaptic Modifications in Cultured Hippocampal Neurons: Dependence on Spike Timing, Synaptic Strength, and Postsynaptic Cell Type," J. Neurosci., vol. 18, pp. 10464-10472, 1998.
[71] J. L. Lobo, J. Del Ser, A. Bifet, and N. Kasabov, "Spiking Neural Networks and online learning: An overview and perspectives," Neural Netw, vol. 121, pp. 88-100, Jan 2020.
[72] W. Maass, “Networks of spiking neurons: the third generation of neural network models,” Neural Netw, vol. 10, pp. 1659-1671, 1997.
[73] S. Subhechha, R. Degraeve, P. Roussel, L. Goux, S. Clima, K. De Meyer, et al., "Kinetic defect distribution approach for modeling the transient, endurance and retention of a-VMCO RRAM," in Proc. IEEE Int. Rel. Phys. Symp. (IRPS), 2017, pp. 5A-5.1-5A-5.6.
[74] J. Ma, Z. Chai, W. Zhang, B. Govoreanu, J. F. Zhang, Z. Ji, et al., "Identify the critical regions and switching/failure mechanisms in non-filamentary RRAM (a-VMCO) by RTN and CVS techniques for memory window improvement," in Proc. Int. Electron Devices Meeting (IEDM), 2016, pp. 21.4.1-21.4.4.
[75] N. C. Das, S.-I. Oh, J. R. Rani, S.-M. Hong, and J.-H. Jang, "Multilevel Bipolar Electroforming-Free Resistive Switching Memory Based on Silicon Oxynitride," Appl. Sci., vol. 10, p. 3506, 2020.
[76] L. Liu, Y. Hou, B. Chen, B. Gao, and J. Kang, "Improved unipolar resistive switching characteristics of mixed-NiOx/NiOy-film-based resistive switching memory devices," Jpn. J. Appl. Phys., vol. 54, p. 094201, 2015.
[77] S. Dhar and A. H. Marshak, "Static dielectric constant of heavily doped semiconductors," Solid-state electron., vol. 28, no. 8, pp. 763-766, 1985.
[78] S. D. Ristić, Z. D. Prijić, and S. Ž. Mijalković, "The effect of impurity concentration dependent static dielectric constant on band band-gap narrowing in heavily doped silicon," Phys. Stat. Sol. (a), vol. 148, pp. 575 -584, 1995.
[79] P. D. Roberts and C. C. Bell, "Spike timing dependent synaptic plasticity in biological systems, " Biol. Cybern., vol. 87, pp. 392-403, 2002.
[80] C. Zamarreño-Ramos, L. A. Camuñas-Mesa, J. A. Pérez-Carrasco, T. Masquelier, T. Serrano-Gotarredona, t al., "On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex," Front. Neurosci., vol. 5, 26, 2011.
[81] P. U. Diehl and M. Cook, "Unsupervised learning of digit recognition using spike-timing-dependent plasticity." Front. Comput. Neurosci., vol. 9, 99, 2015.
[82] G. Pedretti, S. Bianchi, V. Milo, A. Calderoni, N. Ramaswamy, et al., "Modeling-based design of brain-inspired spiking neural networks with RRAM learning synapses," in Proc. Int. Electron Devices Meeting (IEDM), 2017, pp. 653-656.
[83] F. Ponulak and A. Kasinski, "Supervised learning in spiking neuralnetworks with resume: Sequence learning, classification, and spike shifting," Neural Comput., vol. 22, pp. 467-510, 2010.
[84] S. Yu, et al., "Scaling-up resistive synaptic arrays for neuro-inspired architecture: challenges and prospect," in Proc. Int. Electron Devices Meeting (IEDM),2015, pp. 451-454.
[85] C.-C Chang, J.-C Liu, Y-L. Shen, T. Chou, P.-C Chen, et al., "Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network," in Proc. Int. Electron Devices Meeting (IEDM), 2017, pp. 278-281.
[86] J. H. Yoon, K. M. Kim, S. J. Song, J. Y. Seok, K. J. Yoon, et al., "Pt/Ta2O5/HfO2−x/Ti resistive switching memory competing with multilevel NAND flash," Adv. Mater., vol. 27, pp. 3811-3816, 2015.
[87] D. Duncan, B. Magyari-Kope, and Y. Nishi, "Filament-Induced Anisotropic Oxygen Vacancy Diffusion and Charge Trapping Effects in Hafnium Oxide RRAM," IEEE Electron Device Lett., vol. 37, pp. 400-403, 2016.
[88] D. Kuzum, R. G. Jeyasingh, B. Lee, and H. S. Wong, "Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing," Nano Lett, vol. 12, pp. 2179-86, 2012.
[89] M. Suri, O. Bichler, D. Querlioz, O. Cueto, L. Perniola, V. Sousa, et al., "Phase change memory as synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction," in Proc. Int. Electron Devices Meeting (IEDM), 2011, pp. 4.4.1-4.4.4.
[90] Y. Li, Y. Zhong, L. Xu, J. Zhang, X. Xu, H. Sun, et al., "Ultrafast synaptic events in a chalcogenide memristor," Sci Rep, vol. 3, p. 1619, 2013.
[91] Y. Zhong, Y. Li, L. Xu, and X. Miao, "Simple square pulses for implementing spike-timing-dependent plasticity in phase-change memory," Phys. Status Solidi. Rapid Res. Lett., vol. 9, pp. 414-419, 2015.
[92] H. Tian, X. Cao, Y. Xie, X. Yan, A. Kostelec, D. DiMarzio, et al., "Emulating Bilingual Synaptic Response Using a Junction-Based Artificial Synaptic Device," ACS Nano, vol. 11, pp. 7156-7163, 2017.
[93] G. W. Burr et al., "Experimental demonstration and tolerancing of a large-scale neural network (165,000 synapses), using phase-change memory as the synaptic weight element," in Proc. Int. Electron Devices Meeting (IEDM), 2014, pp. 697-700.
[94] P. O’Connor and M. Welling, "Deep spiking networks," arXiv:1602.08323, pp. 1-16, 2016.
[95] C. W. Hsu, C. C. Wan, I. T. Wang, M. C. Chen, C. L. Lo, Y. J. Lee, et al., "3D vertical TaOx/TiO2 RRAM with over 103 self-rectifying ratio and sub-μA operating current " in Proc. Int. Electron Devices Meeting (IEDM), 2013, pp. 10.4. 1-10.4. 4.
[96] B. Govoreanu, D. Crotti, S. Subhechha, L. Zhang, Y. Y. Chen, S. Clima, et al., "A-VMCO: A novel forming-free, self-rectifying, analog memory cell with low-current operation, nonfilamentary switching and excellent variability," in Proc. Symp. VLSI Technol. (VLSIT), 2015, pp. T132-T133.
[97] Q. Luo, X. Xu, H. Liu, H. Lv, T. Gong, S. Long, et al., "Super non-linear RRAM with ultra-low power for 3D vertical nano-crossbar arrays" Nanoscale, vol. 8, pp. 15629-15636, 2016.
[98] C. Li, L. Han, H. Jiang, M. H. Jang, P. Lin, Q. Wu, et al., "Three-dimensional crossbar arrays of self-rectifying Si/SiO2/Si memristors," Nat. Commun., vol. 8, 15666, 2017.
[99] S. Pi, C. Li, H. Jiang, W. Xia, H. Xin, J. J. Yang, et al., "Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension," Nat. Nanotechnol., vol. 14, pp. 35-39, 2019.
[100] C.-T. Chou, B. Hudec, C.-W. Hsu, W.-L. Lai, C.-C. Chang, and T.-H. Hou, "Crossbar array of selector-less TaOx/TiO2 bilayer RRAM," Microelectron. Reliab., vol. 55, pp. 2220-2223, 2015.
[101] P.-Y. Chen, Z. Li, and S. Yu, "Design tradeoffs of vertical RRAM-based 3-D cross-point array," IEEE Trans. VLSI Syst., vol. 24, no. 12, pp. 3460-3467, 2016.
[102] W. C. Chien, H. Y. Ho, C. W. Yeh, , C. H. Yang, H. Y. Cheng, W. Kim, et al., "Comprehensive scaling study on 3D cross-point PCM toward 1Znm node for SCM applications," in Proc. Symp. VLSI Technol. (VLSIT), 2019, pp. T60-T61.
[103] H. Yang, X. Hao, Z. Wang, R. Malmhall, H. Gan, K. Satoh, et al., " Threshold switching selector and 1S1R integration development for 3D cross-point STT-MRAM," in Proc. Int. Electron Devices Meeting (IEDM), 2017, pp. 38.1.1-38.1.4.
[104] Y. K. Chang, “Investigating Resistive Switching Mechanism of Bilayer RRAM Using Impedance Analysis,” Master thesis, Dept. Electron. Eng., National Chiao Tung University, Hsinchu, Taiwan, 2015.
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