臺灣博碩士論文加值系統

本論文將延續以缺陷為基礎的橋接式故障模型，提出了以缺陷為基礎動態的橋接式故障模型之產生方法。利用工業電路在自動測試圖案產生及故障模擬的結果展示出了以缺陷為基礎的動態橋接式故障的測試圖案數量明顯少於傳統的 4 路優勢動態橋接故障。此外，較多數量的 4 路優勢動態橋接故障測試圖案仍無法檢測到一些基於缺陷的動態橋接故障。最後，我們也提出優先針對較有機會發生短路缺陷的地方來產生橋接故障的方法。

This thesis follows the defect-based bridge fault and proposed a methodology of
dynamic defect-based bridge fault. The result of ATPG and fault simulation based on industrial designs has demonstrated that the number of test patterns generated by dynamic defect-based bridge fault model is significantly smaller than that generated by conventional dynamic 4-way dominance bridge fault mode. Also, some short defects can only be detected by the test set for dynamic defect-based bridge faults but not by the test set for dynamic 4-way dominance bridge faults with more test patterns. Finally, we also proposed a methodology to preferentially simulate the short defect which is more likely to occur.

Abstract (Chinese) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract (English) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Acknowlegement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Defect-Based Bridge Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 1tf Defect-Based Bridge Fault . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 2tf Defect-Based Bridge Fault . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Proposed Framework for Extracting Defect-based Bridge Faults . . . . . . . . . 8
3.1 Flow Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Selection of Defective Resistance . . . . . . . . . . . . . . . . . . . . . . . 10
4 Experiment on 2tf Defect-based Bridge Faults . . . . . . . . . . . . . . . . . . . 12
4.1 Benchmark Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Extraction of 2tf Defect-based Bridge Faults . . . . . . . . . . . . . . . . . 12
4.3 Runtime Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 ATPG Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Generating Top-off Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 15
iv
5 Shorted Pair Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 Critical Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 # SPICE Stimulated Patterns . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Runtime Experiment on 3 Industrial Design . . . . . . . . . . . . . . . . . 19
6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

[1] S. Mandava, S. Chakravarty and S. Kundu“On Detecting Bridges Causing Timing
Failures,＂in 1999 IEEE International Conference on Computer Design: VLSI in
Computers and Processors (ICCD), Oct. 1999, pp. 1–7
[2] M. Renovell, P. Huc, and Y. Bertrand “CMOS Bridging Fault Modeling,＂in 1994
IEEE VLSI Test Symposium (VTS), April. 1994, pp. 1–6
[3] M. Abramovici, P. R. Mtnon, “A Practical Approach to Fault Simulation and Test
Generation for Bridging Faults,＂in 1985 IEEE Transactions on Computers, July
1985, pp. 658–663
[4] S. Millman, J. Garvey “An Accurate Bridging Fault Test Pattern Generator,＂in
1991 IEEE International Test Conference (ITC), Oct 1991, pp. 1–10
[5] N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. Reddy, I. Pomeranz, ”A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults,”
in 2005 IEEE European Test Symposium (ETS), May 2005, pp. 1–6
[6] J.P. Cusey, J.H. Patel “BART: a Bridging Fault Test Generator for Sequential
Circuits,＂in 1997 IEEE International Test Conference (ITC), Nov 1997, pp. 1–10
23
[7] P. Maxwell, F. Hapke, M. Ryynanen and P. Weseloh, “Bridge over Troubled Waters: Critical Area Based Pattern Generation,＂in 2017 22nd IEEE European Test
Symposium (ETS), May 2017, pp. 1–6
[8] Tessent Scan and ATPG User’s Manual, v2017.3 ed., Mentor Graphics Corporation,
September 2017.
[9] TetraMAX® ATPG User Guide, N-2017.09, Synopsys Corporation, Sep 2017
[10] A. V. Ferris-Prabhu, “Modeling The Critical Area in Yield Forecasts,＂in IEEE
Journal of Solid-State Circuits, Aug. 1985, pp. 874–878
[11] J.P.D. Gyvez and J.A.G. Jess,“On the definition of critical areas for IC photolithographic spot defects,＂in 1989 Proceedings of the 1st European Test Conference, April.
1989, pp. 152—158
[12] S. Fitzpatrick, G. O’Donoghue and G. Cheek,“A Comparison of Critical Area Analysis Tools,＂in 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
and Workshop, Sept. 1998, pp. 31—33
[13] E. Papadopoulou and D. T. Lee,“Critical area computation via Voronoi diagrams,＂
in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
April. 1999, pp. 463—474
[14] C. H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,＂in 1983 IBM
Journal of Research and Development, Nov. 1983, pp. 549–557
[15] T. Iizuka, M. Ikeda and K. Asada, “Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells,＂in 2004 IEEE International
Symposium on Signals, Circuits and Systems (SCS), Mar. 2004, pp. 337–380
24
[16] P. Vijayakumar, V. B. Suresh and S. Kundu, “Lithography Aware Critical Area
Estimation and Yield Analysis,＂in 2011 IEEE International Test Conference, Sept.
2011, pp. 1–8
[17] F. Hapke and P. Maxwell, “Total Critical Area Based Testing,” in Proceedings International Test Conference 2018 (ITC), November 2018.
[18] F. Hapke, R. Krenz-Baath, A. Glowatz, J. Schloeffel, H. Hashempour, S. Eichenberger, C. Hora, and D. Adolfsson, “Defect-oriented cell-aware atpg and fault simulation for industrial cell libraries and designs,” in 2009 International Test Conference,
Nov 2009, pp. 1–10.
[19] Y. Huang, C. Lu, T. Wu, Y. Nien, Y. Chen, M. Wu, J. Lee, and M. Chao, “Methodology of Generating Dual-Cell-Aware Tests,” in 2017 IEEE 35th VLSI Test Symposium
(VTS), April 2017, pp. 1–6.
[20] Tessent® CellModelGen Tool Reference, v2017.3 ed., Mentor Graphics Corporation,
September 2017.
[21] F. Hapke et al., “Cell-aware production test results from a 32-nm notebook processor,” in 2012 IEEE International Test Conference, Nov 2012, pp. 1–9.
[22] F. Hapke et al., “Cell-aware experiences in a high-quality automotive test suite,” in
2014 19th IEEE European Test Symposium (ETS), May 2014, pp. 1–6.
[23] W. Howell, F. Hapke, E. Brazil, S. Venkataraman, R. Datta, A. Glowatz, W. Redemund, J. Schmerberg, A. Fast, J. Rajsk, “DPPM Reduction Methods and New
Defect Oriented Test Methods Applied to Advanced FinFET Technologies ,＂in 2018
IEEE International Test Conference (ITC), NOV. 2018, pp. 1–10
25
[24] T. Wu, D. Lee, K. Wu, Y. Huang, Y. Chen, P. Chen, M. Chern, J. Lee, S. Kao,
and M. Chao “Layout-Based Dual-Cell-Aware Tests,” in 2019 IEEE 35th VLSI Test
Symposium (VTS), April 2019, pp. 1–6.
[25] Y. Hu, S. Chang, K. Wu, C. Wang, F. Huang, Y. Tang, Y. Chen, M. Chen, and
M. Chao “Test Methodology for Defect-based Bridge Faults,” in 2020 IEEE International Test Conference in Asia (ITC-Asia), Sept. 2020, pp. 106–111.