臺灣博碩士論文加值系統

隨著先進技術的發展，用於無線通信的智能傳感測器已成為物聯網應用中的關鍵組成部分。部署在環境中的大量感測節點使得更換電池變得難以執行。對於低吞吐量的應用，利用喚醒接收器(wake-up receiver)在需要時喚醒主收發器是個有效的方法。因此，高性能和高功率的主收發器可以在大多數時間保持睡眠模式以節省功率，而使用能量檢測(energy detection)實現的喚醒接收器是此類低功耗操作的最佳選擇。
本文提出了一種基於能量檢測的喚醒接收機的設計，並採用台積電90奈米CMOS技術製造。在RF前端皆為被動電路的情況下，所有電路均以基帶頻率工作，因此在0.5 V電源電壓下的總功耗為3.6 nW。透過使用開關電容器積分器(switched-capacitor integrator)代替交流耦合電阻和電容進行偏移補償來減小面積，而晶片面積為0.84 mm2。該接收器以427.8-MHz ISM頻段和100 b/s的數據速率運行，靈敏度為75.3 dBm 時延遲為110毫秒，適合短距離IoT應用。

Smart sensors for wireless communication is a key building block in IoT applications. A large number of sensor nodes deployed in the environment makes battery replacement impracticable. Utilizing wake-up receiver to wake up the main transceiver when required is an efficient way for low-throughput applications. Thus, the high-performance and high-power main transceiver can maintain at sleeping mode most of the time to save power. Wake-up receivers realized using energy-detection are the best choice for such low-power operations.
This thesis presents the design of a wake-up receiver based on energy detection. The proposed chip is fabricated in TSMC 90-nm CMOS technology. With a passive front end, all the circuits are operating at baseband frequency, leading to a total power consumption of 3.6 nW under a 0.5-V supply voltage. The chip occupies 0.84-mm2 area, which is reduced by using switched-capacitor integrator instead of ac-coupling resistors and capacitors for offset compensation. Operating at 427.8-MHz ISM-band and 100-b/s data rate, the receiver has a sensitivity of −75.3 dBm with a 110-ms latency, which is suitable for short-range IoT applications.

中文審定書 i
英文審定書 ii
摘要 v
Abstract vi
List of Figures ix
List of Tables xiii
Chapter 1 Introduction 1
1.1 Wake-Up Receivers 2
1.1.1 Battery Lifetime 3
1.1.2 False-Alarm Rate 3
1.1.3 Wake-Up Latency 4
1.1.4 Carrier Frequency and Link Budget 4
1.2 Architectures of Sub-μW Wake-Up Radios 5
1.2.1 Heterodyne Receiver 5
1.2.2 Mixer-based Uncertain-IF Receiver 6
1.2.3 Tuned-RF Receiver 7
1.2.4 Direct Energy-Detecting Receiver 8
1.3 Operation Scheme 9
1.3.1 Bit-Level Duty-Cycling 9
1.3.2 Packet-Level Duty-Cycling 10
1.3.3 Always-On Wake-Up Receivers 11
1.4 Thesis Organization 11
Chapter 2 Noise and Sensitivity Analysis for Energy-detecting Receivers 12
2.1 SNR Analysis 12
2.2 Envelope Detector Model 15
2.3 Sensitivity Analysis 17
2.3.1 Self-Mixing of Antenna Noise Dominates 17
2.3.2 Antenna Noise Mixed with Input Signal Dominates 18
2.3.3 Sensitivity and Front-end Gain 18
2.4 Impact of Insufficient Front-End Gain 20
2.5 Optimizing for Sensitivity 21
Chapter 3 Envelope Detectors 23
3.1 Conventional Envelope Detectors 23
3.1.1 Active Detector Modeling 24
3.1.2 Passive Detector Modeling 25
3.1.3 Passive vs. Active Envelope Detectors 28
3.2 Satisfying the Design Requirements 29
3.2.1 Achieving Desired Resistance 30
3.2.2 Minimizing Capacitance 31
3.3 Multi-Stage Design 32
3.3.1 Characteristic of Multi-Stage Envelope Detector 32
3.3.2 Conversion Gain Enhancement 34
3.3.3 Sensitivity 35
3.3.4 Bandwidth 36
3.3.5 Biasing Circuit 37
Chapter 4 Proposed Low-power Wake-up Receiver Based on Energy Detection 38
4.1 Design Challenge 38
4.2 Receiver Architecture 40
4.3 Circuit Implementation 42
4.3.1 RF Front End 42
4.3.2 Baseband Voltage Amplifier 44
4.3.3 Comparator Design 46
4.3.4 Digital Correlator 50
4.3.5 Bias Circuits and Clock Source 51
4.3.6 Switched-Capacitor Integrator for DC Feedback 53
4.4 System Analysis 55
4.4.1 Offset 55
4.4.2 Sensitivity 56
Chapter 5 Measurement Results and Future Works 62
5.1 Measurement Environment Setup 62
5.2 Measurement Results 63
5.3 Conclusion and Comparison Table 68
5.4 Future Works 70
References 71

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