臺灣博碩士論文加值系統

本論文提出了三個應用於微波及毫米波系統的關鍵放大器，其所使用的製程皆為90奈米互補式金氧半電晶體(CMOS FET)製程，第一個為低功耗且小晶片面積的高增益寬頻可變增益分散式放大器。第二個為創新且晶片核心面積小的變壓器匹配之無開關雙向功率低雜訊放大器。最後一個為應用於E頻帶的可變增益低雜訊放大器。
首先提出的放大器以混和傳統分散式放大器(CDA)以及串接單級分散式放大器(CSSDA)為架構，並以疊接放大器(cascode amplifier)為其中的增益元件，再利用主動終端可變電阻(AVTR)來達到平坦增益度之可變增益分散式放大器。其中增益頻寬積(GBW product)、直流功耗、增益控制範圍以及晶片面積為此可變增益分散式放大器的重要考量。在利用主動終端可變電阻的情形下，其增益平坦度可以做到有效的調整，且不會有增加直流功耗以及占用晶片面積之問題。此可變增益分散放大器達到21 dB的小訊號增益、40 GHz的3-dB頻寬以及18 dB的增益控制範圍，且直流功耗在最高的增益狀態僅有32.9 mW，而晶片的總面積只有0.72平方毫米。
接著是設計於Ka頻段基於變壓器架構之無開關雙向功率低雜訊放大器(switchless bidirectional PA-LNA)，其採用了創新的雙向變壓器匹配網路來達到虛擬開關(virtual switch)之效果，以取代傳統的單刀雙擲開關(SPDT switch)電路，如此一來不僅能保有功率放大器以及低雜訊放大器原有之特性，還可以達到節省晶片面積之效果。此功率低雜訊放大器在功率放大器模式下達到18.1 dB的小訊號增益、9.5 GHz的3-dB頻寬以及在33 GHz的操作頻率下達到15.2 dBm的飽和輸出功率、29 %之最高功率附加效率。在低雜訊放大器模式下達到18.1 dB的小訊號增益、4.2 GHz的3-dB頻寬以及在35 GHz的操作頻率下達到最小4.5 dB的雜訊指數，而在3-dB頻寬下達到4.8 dB的平均雜訊指數。此晶片的核心面積只有0.21平方毫米。
最後提出的是應用於E頻段的可調增益低雜訊放大器，其電路由兩級的電流再利用(current-reused)架構串聯一級疊接放大器以及一級電流導引(current-steering)結構的放大器所組合而成。其中小訊號增益、直流功耗以及增益調控範圍為設計此放大器之考量。利用電流共享架構以及增益增強技術，此可調增益低雜訊放大器可以達到26.1 dB的小訊號增益和14.1 GHz的3-dB頻寬，在78 GHz的操作頻率下達到最小4.8 dB的雜訊指數以及17 dB的增益控制範圍，而在3-dB頻寬下達到5.4 dB的平均雜訊指數。此外其直流功率僅消耗23 mW且此晶片的整體面積只有0.52平方毫米。

This thesis proposes three essential amplifiers implemented in the 90-nm complementary metal oxide semiconductor (CMOS) FET process for microwave and millimeter-wave (mm-wave) systems. The first part is high-gain and wideband variable gain distributed amplifier (VGDA) with low power dissipation and small chip area. The second part is an innovative and small core area of the transformer (TF)-based switchless bidirectional power amplifier-low noise amplifier (PA-LNA). The last part is an E-band low-power consumption variable gain-low noise amplifier (VG-LNA).
The first proposed amplifier is based on a conventional distributed amplifier (CDA) with cascaded single-stage distributed amplifier (CSSDA) in cascaded and employed cascode amplifier as the gain unit. Furthermore, the active variable termination resistor (AVTR) is adopted to achieve flat gain performance of VGDA. Among them, gain bandwidth product (GBW), dc power dissipation, gain control range, and chip area are important considerations for VGDA. In the case of using AVTR, its gain flatness can be effectively adjusted without increasing dc power consumption and occupying any additional chip area. This VGDA achieves a small-signal gain of 21-dB with a 40-GHz 3-dB bandwidth and 18-dB gain control range. The DC power consumption in the highest gain state is 32.9 mW and the total area of this chip is only 0.72 mm2.
The second amplifier is the switchless bidirectional power amplifier-low noise amplifier (PA-LNA) designed in Ka-band based on TF architecture. The PA-LNA employs an innovative bidirectional TF matching network as the virtual switch to replace the traditional single-pole double-throw (SPDT) switch. As a side benefit, avoiding the use of the SPDT switches not only saves the chip area, but also maintains the original performance of PA and LNA modes. This PA-LNA achieves 18.1-dB peak small-signal gain in both PA and LNA modes. In the PA mode, it achieves the measured peak saturated output power (Psat) of 15.2 dBm with 29% peak power-added efficiency (PAEMAX) at 33 GHz, while LNA mode achieves a minimum noise figure of 4.5 dB at 35 GHz and an average noise figure of 4.8 dB in a 3-dB bandwidth. The core area of this chip is only 0.21 mm2.
The last one is a variable gain-low noise amplifier (VG-LNA) applied to the E-band communication systems. This VG-LNA consists of a two-stage current-reused amplifier with a one-stage cascode amplifier and one-stage current-steering amplifier in cascaded. Among them, small-signal gain, dc power dissipation, and gain control range are main considerations for designing this amplifier. By adopting current-reused topology and gain enhancement techniques, this VG-LNA can achieve a 26.1-dB peak small-signal gain with 14.1-GHz 3-dB bandwidth, 17-dB gain control range, 4.8-dB minimum noise figure at 78 GHz, and an average noise figure of 5.4 dB in a 3-dB bandwidth. Besides, the power consumption is only 23 mW, and the total area of this chip is only 0.52 mm2.

誌謝 i
中文摘要 ii
ABSTRACT iv
CONTENTS vi
LIST OF FIGURES x
LIST OF TABLES xix
Chapter 1 Introduction 1
1.1 Backgrounds and Motivations 1
1.2 Literature Survey 4
1.2.1 Wideband VGAs 4
1.2.2 Switchless bidirectional PA-LNAs 5
1.2.3 High-Frequency LNAs and VG-LNAs 7
1.3 Contributions 9
1.3.1 Ultra-Wideband VGDA 9
1.3.2 Switchless Bidirectional PA-LNA 9
1.3.3 E-band High Gain VG-LNA 10
1.4 Thesis Organization 11
Chapter 2 Design of a Variable Gain Distributed Amplifier with Low Power Consumption in 90-nm CMOS Process 12
2.1 Classification of Distributed Amplifier Architecture 13
2.1.1 Conventional Distributed Amplifier [37] 13
2.1.2 Cascaded Single-Stage Distributed Amplifier [40] 15
2.1.3 Cascaded Multi-Stage Distributed Amplifier [41] 17
2.1.4 Matrix Distributed Amplifier [42] 18
2.1.5 Distributed Amplifier with Cascaded Gain Stages [38] 20
2.1.6 Distributed Amplifier with Internal Feedback [43] 21
2.2 Techniques of Distributed Amplifiers for Performance Enhancement 23
2.2.1 Configurations of Unit Gain Cell 23
2.2.2 Capacitive Division Technique [37] 25
2.2.3 M-Derived Technique [45] [46] 27
2.2.4 Inter-stage Termination Removed Technique [47] 29
2.3 Design of Proposed Variable Gain Distributed Amplifier [33] 30
2.3.1 Basic Circuit Concept 30
2.3.2 Device Size and Bias Selections 32
2.3.3 Design of CDA Stage 35
2.3.4 Design of CSSDA Stage 40
2.3.5 Active Variable Termination Resistor [77] 42
2.3.6 Complete Circuit Schematic and Simulation Results 47
2.4 Experimental Results 53
2.5 Summary 60
Chapter 3 Design of a Ka-band Transformer-Based Switchless Bidirectional PA-LNA in 90-nm CMOS Process [34] 62
3.1 Phased-Array System [5]-[7] 63
3.2 Design Concepts of PA-LNA 65
3.2.1 Amplifier Structure of PA and LNA cores 65
3.2.2 Bidirectional Matching Network 67
3.2.3 PA-LNA Design Trades 68
3.3 Design of PA 72
3.3.1 Block Diagram and Power Budget 72
3.3.2 Device and Bias Selection 72
3.3.3 Driver Stage Design 76
3.3.4 Capacitive Neutralization Technique 77
3.3.5 Matching Networks 80
3.3.6 Circuit Schematic and OFF-state Impedance Check 83
3.4 Design of LNA 85
3.4.1 Matching Network 86
3.4.2 OFF-state Impedance Check 90
3.5 Complete Switchless Bidirectional PA-LNA 93
3.6 Simulated Results of PA-LNA 95
3.7 Fabrication and Experimental Results 102
3.7.1 Digital Modulation 110
3.8 Method to Deal with Common Mode Oscillation of RFIC [63] [78] 114
3.8.1 Common Mode Stability Analysis 114
3.8.2 Common Mode Oscillation Experiment and Debugging 117
3.9 Summary 124
Chapter 4 Design of an E-band Variable Gain Low Nosie Amplifier with High Gain and Low-Power Dissipation in 90-nm CMOS Process 125
4.1 Design Concepts 126
4.1.1 Noise Reduction Technique [64] 127
4.1.2 Gm-Boosting Technique [65] 131
4.1.3 Body-Floating Technique [16] 133
4.1.4 Current-Reused Topology [66] 136
4.1.5 Current-Steering Topology [71] 137
4.2 Circuit Implementation of the E-band VG-LNA 140
4.3 Fabrication and Experimental Results 146
4.4 Summary 153
Chapter 5 Conclusions 155
REFERENCES 157

[1]D. M. Pozar, Microwave Engineering, 3rd Ed. New York: Wiley, 1998.
[2]K. Chang, RF and Microwave Wireless Systems, New York: Wiley, 2000.
[3]FCC website [Online] https://www.fcc/gov/
[4]3GPP website [Online] https://www.3gpp.org/
[5]Y. Wang et al, "A 39-GHz 64-element phased-Array transceiver with built-in phase and amplitude calibrations for large-array 5G NR in 65-nm CMOS," in IEEE J. Solid-State Circuits (JSSC), vol. 55, no. 5, pp. 1249-1269, May 2020.
[6]C. -N. Chen et al, "38-GHz phased array transmitter and receiver based on scalable phased array modules with endfire antenna arrays for 5G MMW data links," in IEEE Trans. Microw. Theory Techn., vol. 69, no. 1, pp. 980-999, Jan. 2021.
[7]C. Chu et al., "A Ka-band scalable hybrid phased array based on four-element ICs," in IEEE Trans. Microw. Theory Techn., vol. 68, no. 1, pp. 288-300, Jan. 2020.
[8]W. Lee and S. Hong, "Low-loss and small-size 28 GHz CMOS SPDT switches using switched inductor," 2018 IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Philadelphia, PA, USA, 2018, pp. 148-151.
[9]S. Jang, S. Kong, H. Lee, J. Park, K. Kim and K. Lee, "28 GHz 1.8 dB insertion loss SPDT switch with 24 dB isolation in 65 nm CMOS," 2018 48th European Microwave Conference (EuMC), Madrid, Spain, 2018, pp. 835-838.
[10]S. Jang, S. Kong, H. -D. Lee, J. Park, K. -S. Kim and B. Park, "A 28 GHz >30 dBm output P1dB SPDT switch with integrated ESD protection in CMOS 65 nm," in Proc. IEEE Eur. Microw. Conf. (EuMC), Jan. 2021.
[11]D. Kim, D. Lee, S. Sim, L. Jeon and S. Hong, "An X-band switchless bidirectional GaN MMIC amplifier for phased array systems," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 24, no. 12, pp. 878-880, Dec. 2014.
[12]F. Meng et al., "A compact 57–67 GHz bidirectional LNAPA in 65-nm CMOS technology," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 26, no. 8, pp. 628-630, Aug. 2016.
[13]A. Gadallah, M. H. Eissa, D. Kissinger and A. Malignaggi, "A V-band miniaturized bidirectional switchless PALNA in SiGe:C BiCMOS technology," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 30, no. 8, pp. 786-789, Aug. 2020.
[14]J. Pang et al., "21.1 A 28GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-Polarized MIMO for 5G NR," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2019.
[15]Che-Chung Kuo, Zuo-Min Tsai, Jeng-Han Tsai and Huei Wang, "A 71–76 GHz CMOS variable gain amplifier using current steering technique," 2008 IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Atlanta, GA, USA, 2008, pp. 609-612.
[16]Y. Wang, C. Chen, Y. Wu and H. Wang, "An E-band variable gain low noise amplifier in 90-nm CMOS process using body-floating and noise reduction techniques," in Proc. IEEE Eur. Microw. Conf. (EuMC), Sept. 2018.
[17]J. Tsai and C. Lin, "A 40-GHz 4-bit digitally controlled VGA with low phase variation using 65-nm CMOS process," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 29, no. 11, pp. 729-732, Nov. 2019.
[18]S. H. Kim, T. H. Jang, J. H. Kim and C. S. Park, "A wideband 120-GHz variable gain amplifier with multistage phase compensation," in IEEE Trans. Microw. Theory Techn., vol. 68, no. 6, pp. 2419-2427, June 2020.
[19]H. Gao et al., "A 6.5–12-GHz balanced variable-gain low-noise amplifier with frequency-selective gain equalization technique," in IEEE Trans. Microw. Theory Techn., vol. 69, no. 1, pp. 732-744, Jan. 2021.
[20]M. Elkholy, S. Shakib, J. Dunworth, V. Aparin and K. Entesari, "A wideband variable gain LNA with high OIP3 for 5G using 40-nm bulk CMOS," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 28, no. 1, pp. 64-66, Jan. 2018.
[21]T. Wu, C. Zhao, H. Liu, Y. Wu, Y. Yu and K. Kang, "A 20 ~ 43 GHz VGA with 21.5 dB Gain tuning range and low phase variation for 5G communications in 65-nm CMOS," 2019 IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Boston, MA, USA, 2019, pp. 71-74.
[22]S. N. Ali, M. Aminul Hoque, S. Gopal, M. Chahardori, M. A. Mokri and D. Heo, "A continually-stepped variable-gain LNA in 65-nm CMOS enabled by a tunable-transformer for mm-Wave 5G communications," in IEEE MTT-S Int. Microw. Symp. Dig., Boston, MA, USA, 2019, pp. 926-929.
[23]M. Vigilante and P. Reynaert, "20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2016.
[24]L. Gao and G. M. Rebeiz, "A 22–44-GHz phased-array receive beamformer in 45-nm CMOS SOI for 5G applications with 3–3.6-dB NF," in IEEE Trans. Microw. Theory Techn., vol. 68, no. 11, pp. 4765-4774, Nov. 2020.
[25]A. A. Nawaz, J. D. Albrecht and A. Çağrı Ulusoy, "A 28-/60-GHz band-switchable bidirectional amplifier for reconfigurable mm-wave transceivers," in IEEE Trans. Microw. Theory Techn., vol. 68, no. 7, pp. 3197-3205, July 2020.
[26]M. Cho, J. Kim and D. Baek, "A switchless CMOS bi-directional distributed gain amplifier with multi-octave bandwidth," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 23, no. 11, pp. 611-613, Nov. 2013.
[27]G. Feng et al., "Pole-converging intrastage bandwidth extension technique for wideband amplifiers," in IEEE J. Solid-State Circuits (JSSC), vol. 52, no. 3, pp. 769-780, March 2017.
[28]J. Tsai, C. Hung, J. Cheng, C. Lin and R. Chang, "An E-band transformer-based 90-nm CMOS LNA," in Proc. IEEE Asia-Pacific Microw. Conf. (APMC), Nov. 2018.
[29]G. Feng, C. C. Boon, F. Meng, X. Yi and C. Li, "An 88.5–110 GHz CMOS low-noise amplifier for millimeter-wave imaging applications," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 26, no. 2, pp. 134-136, Feb. 2016.
[30]L. Gao, E. Wagner and G. M. Rebeiz, "Design of E- and W-band low-noise amplifiers in 22-nm CMOS FD-SOI," in IEEE Trans. Microw. Theory Techn., vol. 68, no. 1, pp. 132-143, Jan. 2020.
[31]D. Pan, Z. Duan, S. Chakraborty, L. Sun and P. Gui, "A 60–90-GHz CMOS double-neutralized LNA technology with 6.3-dB NF and −10dBm P−1dB," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 29, no. 7, pp. 489-491, July 2019.
[32]C. -J. Liang et al., "A 0.6-V VDD W-band neutralized differential low noise amplifier in 28-nm bulk CMOS," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 31, no. 5, pp. 481-484, May 2021.
[33]T. -Y. Chiu, Y. Wang and H. Wang, "A 3.7–43.7-GHz low-power consumption variable gain distributed amplifier in 90-nm CMOS," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 31, no. 2, pp. 169-172, Feb. 2021.
[34]T. -Y. Chiu, Y. Wang and H. Wang, "A Ka-band transformer-based switchless bidirectional PA-LNA in 90-nm CMOS process," in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2021.
[35]F. Zhang and P. Kinget, "Low power programmable-gain CMOS distributed LNA for ultra-wideband applications," Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005., Kyoto, Japan, 2005.
[36]P. Chen, Z. Liao, C. Kuo and H. Wang, "A variable gain distributed amplifier with low voltage and low power in 0.18-μm CMOS technology," in Proc. IEEE Eur. Microw. Conf. (EuMC), Oct. 2011.
[37]R.-C. Liu, T.-P. Wang, L.-H. Lu, H. Wang, "An 80GHz travelling-wave amplifier in a 90nm CMOS technology," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2005.
[38]J. Chien and L. Lu, "40-Gb/s high-gain distributed amplifiers with cascaded gain stages in 0.18-μm CMOS," IEEE J. Solid-State Circuits (JSSC), vol. 42, no. 12, pp. 2715-2725, Dec. 2007.
[39]T. Huang, Y. Lin, J. Cheng, J. Kao, T. Huang and H. Wang, "A high-gain low-noise distributed amplifier with low DC power in 0.18-µm CMOS for vital sign detection radar," in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2015.
[40]Ming-Da Tsai, Kuo-Liang Deng, Huei Wang, Chun-Hung Chen, Chih-Sheng Chang and J. G. J. Chern, "A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 14, no. 12, pp. 554-556, Dec. 2004.
[41]Ming-Da Tsai, Huei Wang, Jui-Feng Kuan and Chih-Sheng Chang, "A 70 GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2005.
[42]J. Chien, T. Chen and L. Lu, "A 9.5-dB 50-GHz matrix distributed amplifier in 0.18-μm CMOS," 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 2006, pp. 146-147.
[43]A. Arbabian, A. M. Niknejad, "A broadband distributed amplifier with internal feedback providing 660GHz GBW in 90nm CMOS," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2008.
[44]J. Kim, "A wideband triple-stacked CMOS distributed power amplifier using double inductive peaking," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 29, no. 12, pp. 787-790, Dec. 2019.
[45]A. Kopa and A. B. Apsel, "Alternative m-derived termination for distributed amplifiers," in IEEE MTT- Int. Microw. Symp. Dig., Jun. 2009.
[46]H. Chang, Y. Liu, S. Weng, C. Lin, Y. Yeh and Y. Wang, "Design and Analysis of a DC–43.5-GHz Fully Integrated Distributed Amplifier Using GaAs HEMT–HBT Cascode Gain Stage," in IEEE Trans. Microw. Theory Techn., vol. 59, no. 2, pp. 443-455, Feb. 2011.
[47]J. Kao, P. Chen, P. Huang and H. Wang, "A novel distributed amplifier with high gain, low noise, and high output power in 0.18-µm CMOS technology,” in IEEE Trans. Microw. Theory Techn., vol. 61, no. 4, pp. 1533-1542, Apr. 2013.
[48]B. Razavi, Design of Analog CMOS Intergrated Circuits. New York: McGraw-Hill, 2001.
[49]L. Gao and G. M. Rebeiz, "A 24-43 GHz LNA with 3.1-3.7 dB noise figure and embedded 3-Pole elliptic high-pass response for 5G applications in 22 nm FDSOI," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2019.
[50]Y. Yu et al., "A 21-to-41-GHz high-gain low noise amplifier with triple-coupled technique for multiband wireless applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no.6, pp. 1857-1861, Jun. 2021.
[51]A. H. Aljuhani and G. M. Rebeiz, "A 12.5 mW packaged K-band CMOS SOI LNA with 1.5 dB NF," in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2019.
[52]K. Kibaroglu, M. Sayginer and G. M. Rebeiz, "A low-cost scalable 32-element 28-GHz phased array transceiver for 5G communication links based on a 2 2 beamformer flip-chip unit cell," in IEEE J. Solid-State Circuits (JSSC), vol. 53, no. 5, pp. 1260-1274, May 2018.
[53]A. G. Roy et al., "A 37-40 GHz phased array front-end with dual polarization for 5G MIMO beamforming applications," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2019.
[54]J. Pang et al., "A 28 GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR," in Proc. IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2019.
[55]J. Pang et al., "A 28-GHz CMOS phased-array transceiver based on LO phase-shifting architecture with gain invariant phase tuning for 5G New Radio," in IEEE J. Solid-State Circuits (JSSC), vol. 54, no. 5, pp. 1228-1242, May 2019.
[56]S. C. Cripps, RF Power Amplifiers for wireless Communications. Bostom, MA: Artech House, 2000.
[57]Y. Zhang and P. Reynaert, "A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2017.
[58]C. C. Cheng, "Neutralization and unilateralization," IRE Trans. Circuit Theory, vol. 2, no. 2, pp.138-145, June 1955.
[59]Noel Deferm, Patrick Reynaert, "CMOS Front Ends for Millimeter Wave Wireless Communication Systems," 2015.
[60]C. Chou, Y. Hsiao, Y. Wu, Y. Lin, C. Wu and H. Wang, "Design of a V-band 20-dBm wideband power amplifier using transformer-based radial power combining in 90-nm CMOS," in IEEE Trans. Microw. Theory Techn., vol. 64, no. 12, pp. 4545-4560, Dec. 2016.
[61]W. Lee and S. Hong, "28 GHz RF front-end structure using CG LNA as a switch," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 30, no. 1, pp. 94-97, Jan. 2020.
[62]J. Wang, W. Zhu and Y. Wang, "A 24.25-27.5 GHz front-end module with transformer-based T/R switch for 5-G communications," 2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Hiroshima, Japan, 2020.
[63]Deferm, N., Reynaert, P. "Differential and common mode stability analysis of differential mm-wave CMOS amplifiers with capacitive neutralization," Analog Integr Circ Sig Process 80, 1-12, 2014.
[64]B. Huang, K. Lin and H. Wang, "Millimeter-wave low power and miniature CMOS multicascode low-noise amplifiers with noise reduction topology," in IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3049-3059, Dec. 2009.
[65]H. Hsieh and L. Lu, "A 40-GHz low-noise amplifier with a positive-feedback network in 0.18-μm CMOS," in IEEE Trans. Microw. Theory Techn., vol. 57, no. 8, pp. 1895-1902, Aug. 2009.
[66]Choong-Yul Cha and Sang-Gug Lee, "A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance," in IEEE J. Solid-State Circuits (JSSC), vol. 38, no. 4, pp. 669-672, April 2003.
[67]K. Hadipour, A. Ghilioni, A. Mazzanti, M. Bassi and F. Svelto, "A 40GHz to 67GHz bandwidth 23dB gain 5.8dB maximum NF mm-Wave LNA in 28nm CMOS," in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), May 2015.
[68]Min Huang, J. Tsai and T. Huang, "A 917-µW Q-band transformer-feedback current-reused LNA using 90-nm CMOS technology," in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2012.
[69]Y. Chang and H. Lu, "A V-band low-power digital variable-gain low-noise amplifier using current-reused technique with stable matching and maintained OP1dB," in IEEE Trans. Microw. Theory Techn., vol. 67, no. 11, pp. 4404-4417, Nov. 2019.
[70]S. Kong, H. D. Lee, M. Lee and B. Park, "A V-band current-reused LNA with a double-transformer-coupling technique," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 26, no. 11, pp. 942-944, Nov. 2016.
[71]J. Xiao, I. Mehr and J. Silva-Martinez, "A high dynamic range CMOS variable gain amplifier for mobile DTV tuner," in IEEE J. Solid-State Circuits (JSSC), vol. 42, no. 2, pp. 292-301, Feb. 2007.
[72]Y. Jiang, Z. Tsai, J. Tsai, H. Chen and H. Wang, "A 86 to 108 GHz Amplifier in 90 nm CMOS," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 18, no. 2, pp. 124-126, Feb. 2008.
[73]J. Lee, C. Chen, J. Tsai, K. Lin and H. Wang, "A 68–83 GHz power amplifier in 90 nm CMOS," in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2009.
[74]C. Li, W. Hsieh and T. Chiu, "A flip-chip-assembled W-Band receiver in 90-nm CMOS and IPD technologies," in IEEE Trans. Microw. Theory Techn., vol. 67, no. 4, pp. 1628-1639, April 2019.
[75]C. -L. Ko, C. -H. Li, C. -N. Kuo, M. -C. Kuo and D. -C. Chang, "A 8-mW 77-GHz band CMOS LNA by using reduced simultaneous noise and impedance matching technique," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 2988-2991.
[76]C. -L. Ko, "CMOS millimeter-wave amplifier design," Ph.D. dissertation, Dept. Electron. Eng. Inst. Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan, 2014.
[77]S. -C. Shin, C. -S. Lin, M. -D, Tsai, K. -Y. Lin and H. Wang, "A low-voltage and variable-gain distributed amplifier for 3.1–10.6 GHz UWB systems," in IEEE Microw. Wireless Compon. Lett. (MWCL), vol. 16, no. 4, pp. 179–181, Apr. 2006.
[78]Bo-Ze Lu, "Research of amplifier for astronomical receiver and power amplifier for 5G mobile communications," National Taiwan University Master Thesis, 2020.
[79]N. Bhushan et al., "Industry perspective," in IEEE Wirel. Commun., vol. 24, no. 5, pp. 6-8, Oct. 2017.
[80]S. Dutta et al, "Frame structure design and analysis for millimeter wave cellular systems," in IEEE Trans. Wirel. Commun., vol. 16, no. 3, pp. 1508-1522, Mar. 2017.
[81]G. Berardinelli, K. I. Pedersen, F. Frederiksen and P. Mogensen, "On the guard period design in 5G TDD wide area," 2016 IEEE 83rd Vehicular Technology Conference (VTC Spring), 2016, pp. 1-5.
[82]W. S. Lau, ULSI Front-End Technology, 2017.
[83]Weishow Hsu, private communication.