跳到主要內容

臺灣博碩士論文加值系統

(44.222.64.76) 您好!臺灣時間:2024/06/25 23:17
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:江振磊
研究生(外文):CHIANG, CHEN-LEI
論文名稱:使用變壓器結合及中和電容技術之 Ka-Band CMOS功率放大器
論文名稱(外文):Ka-Band CMOS Power Amplifiers Using Transformer Combined and Neutralization Capacitor Technique
指導教授:王紳
指導教授(外文):WANG, SEN
口試委員:王紳張繼禾廖兆祥陳立勝
口試委員(外文):WANG, SENCHANG, CHI-HOLIAO, CHAO-HSIANGCHEN, LI-SHENG
口試日期:2021-07-14
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2021
畢業學年度:109
語文別:英文
論文頁數:69
中文關鍵詞:ka頻段變壓器結合中和電容毫米波功率放大器
外文關鍵詞:Ka-BandTransformer combinedNeutralization capacitorMillimeter wave (mmW)Power amplifier (PA)
相關次數:
  • 被引用被引用:0
  • 點閱點閱:176
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文主要提出兩種在ka頻段的毫米波功率放大器設計並且利用台積電CMOS 0.18-μm製程製作。第一個是利用變壓器來做為匹配網路及功率結合的功率放大器;第二個為在前者的基礎下,並聯更多的電晶體來提升功率放大器的增益及效率。
內文主要可以分成三大部分:第一部分為自製變壓器分析,根據理論計算與數學計算出此變壓器的頻率響應及S參數。第二部分為設計功率放大器,藉由中和電容與電晶體的特性來改善放大器增益高頻響應不佳的特性。此晶片的面積為0.2 mm2,小訊號增益為5dB,在輸入功率為0 dBm時的功耗126 mW,輸出飽和功率為16 dBm,輸出1 dB增益壓縮點的輸入功率為12.5 dBm,另外功率附加效率為10.3 %。第三部分在前者做了些改善,利用合成線並聯更多的電晶體,藉此達到更高的輸出功率及效率。此晶片的面積為0.28 mm2,小訊號增益為9.5 dB,在輸入功率為0 dBm時的功耗166 mW,輸出飽和功率為15.5 dBm,輸出1 dB增益壓縮點的輸入功率為13 dBm,另外功率附加效率為12.7 %。

This paper presents two designs of millimeter-wave power amplifiers in the ka-band using TSMC's CMOS 0.18-μm process.
This thesis can be divided into three main parts: the first part is the analysis of the home-built transformer, based on theoretical and mathematical calculations of the frequency response and S-parameters of this transformer. The second part is to design a power amplifier to improve the high gain and poor frequency response of the amplifier by neutralizing the capacitance and transistor characteristics. The area of this chip is 0.2 mm2, the small signal gain is 5 dB, the power consumption is 126 mW at 0 dBm input power, the output saturation power is 15 dBm, the input power at 1 dB gain compression point is 12.5 dBm, and the power additive efficiency is 10.3 %. The third part improves on the former by using synthesized lines to parallel more transistors to achieve higher gain and efficiency. This chip has an area of 0.28 mm2, a small signal gain of 9.5 dB, a power consumption of 166 mW at 0 dBm input power, an output saturation power of 15.6 dBm, an input power of 14.7 dBm at the output 1 dB gain compression point, and a power-added efficiency of 12.7 %.

摘 要 i
Abstract ii
誌 謝 iii
Table of Contents iv
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 The Background and Motivation 1
1.2 Thesis Organization 2
Chapter 2 Fundamentals of Power Amplifier 3
2.1 Introduction 3
2.2 Power Amplifier Considerable Parameters 4
2.2.1 Output Power 4
2.2.2 Power-Added Efficiency 4
2.2.3 Linearily and 1-dB Gain Compression Point 5
2.3 Power Combining Techniques 7
2.3.1 Wilkinson Combining 7
2.3.2 Marchand balun Combining 9
2.3.3 Transformer Combining 11
Chapter 3 A Ka-Band CMOS Power Amplifier with Transformer 13
3.1 Introduction 13
3.2 The Basic Theory 15
3.2.1 Floating Body effects 15
3.2.2 Introduction of Neutralization Capacitor 19
3.3 Design of Proposed normal Power Amplifier with Transformer 21
3.3.1 Design Flow 21
3.3.2 Transistors Size Selection 23
3.3.3 Neutralization Capacitor Selection 25
3.3.4 Load-Pull Method 27
3.3.5 Input and Output Transformers 29
3.3.6 Proposed normal Power Amplifier 47
3.3.7 Simulation & Measurement 49
3.4 Design of Proposed enhanced Power Amplifier with Transformer 52
3.4.1 Transistors and Bias Selection 52
3.4.2 Neutralized Capacitor in power stage 52
3.4.3 Transformer combining and matching 54
3.4.4 Experimental Results 61
3.4.5 Implementation & Measurement 64
3.5 Discussion & Summary 66
Chapter 4 Conclusion 69
Reference 70


[1]M. Series, “IMT vision: Framework and Overall Objectives of the Furture Development of IMT for 2020 and Beyond,” Recommendation IT U-R, Rep. M. 2083-0, 2015.
[2]3GPP, “3rd Generation Partnership Project; Technical Specification Group Radio Access Network; New frequency range for NR(24.5-29.5)(Release 15),” June 2018.
[3]邱煥凱、林貴城編著,ADS應用於射頻功率放大器設計與模擬,國立清華大學出版社,臺灣,新竹,05,2014。
[4]C. Y. Law and A.-V. Pham, “A High-Gain 60 GHz Power Amplifier with 20 dBm Output Power in 90 nm CMOS,” Proc. IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 426-427, 2010.
[5]Y. Yoshihara, R. Fujimoto, N. Ono, T. Mitomo, H. Hoshino and M. Hamada, “A 60-GHz CMOS Power Amplifier with Marchand Balun-Based Parallel Power Combiner,” IEEE A-SSCC Dig. Tech. Papers, pp. 121-124, 2008-Nov.
[6]V. Qunaj and P. Reynaert, “A Compact Ka-Band Transformer-Coupled Power Amplifier for 5G in 0.15um GaAs,” 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), Nov. 2019, pp. 1-4.
[7]Z. Liu et al., “A 42–62 GHz Transformer-Based Broadband mm-Wave InP PA with Second-Harmonic Waveform Engineering and Enhanced Linearity,” IEEE Trans. Microw. Theory Techn., vol. 69, no. 1, pp. 756-773, Jan. 2021.
[8]C. Chou, Y. Hsiao, Y. Wu, Y. Lin, C. Wu and H. Wang, “Design of a V -band 20-dBm Wideband Power Amplifier Using Transformer-Based Radial Power Combining in 90-nm CMOS,” IEEE Trans. Microw. Theory Techn., vol. 64, no. 12, pp. 4545-4560, Dec. 2016.
[9]S.-H. Chang, C.-N. Chen and H. Wang, “A Ka-Band Dual-Mode Power Amplifier in 65-nm CMOS Technology,” IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 708-710, Aug. 2018.
[10]Y.-C. Chen, Y.-H. Lin, J.-L. Lin and H. Wang, “A Ka-Band Transformer-Based Doherty Power Amplifier for Multi-Gb/s Application in 90-nm CMOS,” IEEE Microwave and Wireless Components Letters, Nov. 2018.
[11]J. Xia, X.-H. Fang and S. Boumaiza, “60-GHz Power Amplifier in 45-nm SOI-CMOS Using Stacked Transformer-Based Parallel Power Combiner,” IEEE Microwave and Wireless Components Letters, vol. 28, no. 8, pp. 711-713, Aug. 2018.
[12]Y. Chang, B. Lu, Y. Wang and H. Wang, “A Ka-Band Stacked Power Amplifier with 24.8-dBm Output Power and 24.3% PAE in 65-nm CMOS Technology,” 2019 IEEE MTT-S International Microwave Symposium (IMS), pp. 316-319, 2019.
[13]Nai-Chung Kuo, Jui-Chi Kao, Che-Chung Kuo, and Huei Wang, “K-band CMOS Power Amplifier with Adaptive Bias for Enhancement in Back-ff Ehhiciency,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2011, pp. 1-4.
[14]Chi-Cheng Hung, Jing-Lin Kuo, Kun-You Lin, Huei Wang, “A 22.5-dB Gain, 20.1-dBm Output Power K-Band Power Amplifier in 0.18-μm CMOS,” in IEEE RFIC Symp. Dig., June 2010, pp. 557-560.
[15]K.-Y. Kao, et aI., “Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp. 4505- 4519, Dec. 2013.
[16]M. Chan, P. Su, H. Wan, C.-H. Lin, S. K.-H. Fung, A. M. Niknejad, et al., “Modeling the Floating-Body Effects of Fully Depleted Partially Depleted and Body-Grounded SOI MOSFETs,” Solid-State Electron., vol. 48, pp. 969-978, 2004.
[17]J.-K. Wang, etal., “A V-band Power Amplifier with Transformer Combining and Neutralization Technique in 40-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symp., Aug. 2017.
[18]D.M. Pozar, Microwave Engineering, John Wiley & Sons, Taipei, July, 2016.
[19]D. Zhao and P. Reynaert, “A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 10, pp. 2323-2337, Oct. 2013.
[20]S. Shakib, H.-C. Park, J. Dunworth, V. Aparin, and K. Entesari, “A highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 12, pp. 3020-3036, Dec. 2016.
[21]B. Park, S. Jin, D. Jeong, J. Kim, Y. Cho, K. Moon, and B. Kim, “Highly Linear mm-Wave CMOS Power Amplifier,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 12, pp. 4535-4544, Dec. 2016.
[22]Y. Zhang and P. Reynaert, “A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communication in 40nm CMOS,” in IEEE RFIC Symp., July 2017.
[23]K.-C. Chiang, T.-C. Tsai, I. Huang, J.-H. Tsai, and T.-W. Huang, “A 27-GHz Transformer Based Power Amplifier with 513.8-mW/mm2 Output Power Density and 40.7% Peak PAE in 1-V 28-nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., June 2019, pp. 1283-1286.
[24]Z.-J. Huang, B.-W. Huang, K.-Y. Kao, and K.-Y. Lin, “A High-Gain Continuous Class-F Power Amplifier in 90-nm CMOS for 5G Communication,” in 2019 Asia-Pacific Microwave Conference Technical Digest, Dec. 2019.


電子全文 電子全文(網際網路公開日期:20260803)
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊