臺灣博碩士論文加值系統

隨著穿戴式電子產品以及智聯網的蓬勃發展，IC產業也越來越專注在超低電壓、超低功耗、高整合度…等等方面設計，而數位式低壓降線性穩壓器不僅能操作在超低電壓，也因為不需使用外接電感元件故有體積小的優勢，所以較常被使用在可攜式產品中。因此本論文提出 具快速追鎖機制之非同步骨牌式低壓降線性穩壓器，其操作在輸入電壓0.35V而輸出電壓為0.3V，可供給許多系統作使用例如:感測器、類比數位 轉化器、靜態隨機存取記憶體…等等。此研究採用數位式非同步控制迴路，相對於大家熟悉的同步電路先天上設計有些限制與缺點，非同步電路設計由於不需要用到整體時脈(Global Clock)，而有下列優點:低功率消耗、操作速度快、無時脈分配效應(Clock Distribution)、無時脈歪斜效應(Clock Skew)以及不受快速時脈振盪所造成的磁波干�
��(Electro Magnetic Interference, EMI)。為了有更快的電壓追鎖速度，而有了雙迴路、3D電晶體陣列或是二元搜尋法等不同的想法被提出。然而這些電路都有共同的問題就是不論是同步或是非同步的架構，都仍然受限於固定工作週期的限制。此研究將採用數位式骨牌二元搜尋進行電壓追鎖並結合非同步控制迴路設計用於穩壓模式。其中數位式骨牌二元搜尋可以完全不需要固定的工作週期，取而代之的是如同骨牌一般的單向交握訊號傳輸，此交握訊號不是完整周期的訊號，而是只有低電位到高電位的訊號，因此可以省下許多的時間。此電路有以下優點:可操作在超低電壓、低功率消耗、高速的電壓追鎖。而非同步控制迴路能在穩壓模式時降低輸出漣波，輸出更穩定的電壓，並且只需極低的靜態電流。在骨牌式二元搜尋法的追鎖模式下將藉由尺寸較大的二進制�
�率電晶體迅速的提供大量電流以有效的提升整體系統追鎖速率，而在追鎖完成後系統及切換至穩壓模式，透過非同步控制迴路控制小尺寸的功率電晶體達到降低輸出電壓漣波的擺幅的目的。切換兩個迴路則是利用雙緣觸發的電壓誤差偵測器，利用非同步控制單元的交握訊號正負緣作為電壓誤差偵測器的輸入時脈，以達到更快的電壓誤差偵測。本研究預計結合非同步骨牌式二元搜尋電路研製、非同步控制迴路研製、電壓誤差偵測器、負載偵測器、功率電晶體陣列、五大區塊，並且透過分析各個子電路在超低電壓的工作情形，完成具快速追鎖機制之非同步骨牌式低壓降線性穩壓器。

With the development of wearable electronic products and intelligent networking, the IC industry is increasingly focusing on the design of ultra-low voltage, ultra-low power consumption, high integration... etc., and digital low-dropout regulators can not only operating at ultra-low voltage, and because it does not need to use external inductance components, it has the advantage of small size, so it is more often used in wearable products. Therefore, this paper proposes A Fast Settling Asynchronous Low Dropout Regulator with Domino Control Mechanism. It operates at input voltage of 0.35V and an output voltage of 0.3V. This research uses a digital asynchronous control loop, which has some limitations and shortcomings compared to the familiar design of synchronous circuits. Since the design of asynchronous circuits does not need to use the global clock, it has the following advantages: Low power consumption , Fast operating speed, no clock distribu
tion effect, no clock skew and no electromagnetic interference (Electro Magnetic Interference, EMI) caused by fast clock oscillation. In order to have a faster voltage tracking speed, different ideas such as dual loops, 3D transistor arrays, or binary search methods have been proposed. However, these circuits have a common problem that whether they are synchronous or asynchronous architectures, they are still limited by the clock or pulse cycle. In this research, digital domino binary search will be used for voltage tracking and combined with asynchronous control loop designed for voltage regulation mode. The digital domino binary search does not require a work cycle at all. Instead, it is a one-way handshaking signal transmission. This handshaking signal is not a complete cycle signal, but only a signal from low to high potential. , So it can save a lot of time. This circuit has the following advantages: It can be operated at ultra-low voltage, low power consumption, and high-speed
voltage tracking. The asynchronous control loop can reduce the output ripple in the voltage regulation mode and only requires a very low quiescent current. In the tracking mode of the domino binary search method, a large binary power transistor will quickly provide a large amount of current to effectively increase the overall system tracking rate. After the tracking is completed, the system switch to voltage regulation. In this mode, a small-sized power transistor is controlled through an asynchronous control loop to achieve the purpose of reducing the output ripple. To switch between the two loops, a double-edge triggered voltage error detector is used, and the positive and negative edges of the handshake signal of the asynchronous control unit are used as the input clock of the voltage error detector to achieve faster voltage error detection.

致謝 I
中文摘要 III
英文摘要 IV
目錄 V
圖目錄 VIII
表目錄 XI
第一章 緒論 1
1.1 研究背景與動機 1
1.2 論文架構 5
第二章 低壓降線性穩壓器介紹 6
2.1穩壓器的分類 6
2.1.1切換式穩壓器(Switching Regulator) 6
2.1.2切換式電容穩壓器(Switching Capacitance Regulator) 8
2.1.3低壓降線性穩壓器(Low-Dropout Regulator) 9
2.1.4穩壓器比較 11
2.2低壓降線性穩壓器分類 12
2.2.1類比式低壓降線性穩壓器 12
2.2.2數位式同步低壓降線性穩壓器 13
2.2.3數位式非同步低壓降線性穩壓器 14
2.3低壓降線性穩壓器之特性參數 15
2.3.1輸出電壓差 16
2.3.2靜態電流 17
2.3.3線性調節率 18
2.3.4負載調節率 19
2.3.5電源效率 21
2.3.6輸出準確率 21
2.4穩定性分析 23
2.4.1暫態響應 27
2.4.2頻率響應 30
第三章 文獻分析與探討 34
3.1 文獻分析 34
3.1.1 65奈米製程之數位控制低壓降線性穩壓器 34
3.1.2低靜態電流非同步低壓降線性穩壓器 35
3.1.3具雙緣觸發控制之數位式低壓降線性穩壓電路架構 36
3.1.4二元搜尋之同步低壓降線性穩壓器電路架構 37
3.1.5二元搜尋之快閃式非同步低壓降線性穩壓器電路架構 38
3.2 文獻比較 40
第四章 電路設計與模擬 41
4.1具快速追鎖機制之非同步骨牌式低壓降線性穩壓器設計 43
4.1.1 時脈控制之栓鎖比較器 43
4.1.2 七位元非同步骨牌二元搜尋控制迴路 45
4.1.3 電壓誤差偵測器 48
4.1.4六位元可調式非同步雙向控制迴路 49
4.1.5 PMOS電源陣列 51
4.2電路佈局與模擬 54
4.2.1全系統之電路佈局 56
4.2.2全系統之模擬結果 58
第五章 量測考量 66
5.1量測考量 66
5.2量測結果 67
第六章 結論與未來展望 71
參考文獻 72
 
圖目錄
圖1.1智慧手錶電路架構 2
圖1.2同步數位式低壓降線性穩壓器架構 4
圖1.3同步數位式低壓降線性穩壓器特性 4
圖1.4非同步控制示意圖 5
圖2.1切換式穩壓器基本架構 7
圖2.2升壓型切換式電容穩壓器 8
圖2.3低壓降線性穩壓器基本架構 10
圖2.4類比式低壓降線性穩壓器基本架構 12
圖2.5數位式同步低壓降線性穩壓器基本架構 14
圖2.6數位式非同步低壓降線性穩壓器基本架構 15
圖2.7低壓降線性穩壓器之輸入對輸出電壓曲線圖 17
圖2.8靜態電流示意圖 18
圖2.9 低壓降線性穩壓器線性調節率示意圖 19
圖2.10低壓降線性穩壓器負載調節率示意圖 20
圖2.11輸出電壓誤差示意圖 22
圖2.12誤差放大器偏移示意圖 23
圖2.13電阻值誤差示意圖 23
圖2.14應用於SoC內的補償方式 26
圖2.15利用DFC調整相位邊限 26
圖2.16低壓降線性穩壓器與輸出電容及負載電流 27
圖2.17低壓降線性穩壓器輸出對負載電流反應圖 28
圖2.18低壓降線性穩壓器之交流分析等效模型 30
圖2.19等效串聯電阻過大與過小之影響 32
圖3.1 65奈米製程之數位控制低壓降線性穩壓器 35
圖3.2低靜態電流非同步低壓降線性穩壓器 36
圖3.3(a)雙緣觸發之同步架構 37
圖3.3(b)單緣觸發之同步架構 37
圖3.4二元搜尋之同步低壓降線性穩壓器 38
圖3.5 二元搜尋之快閃式非同步架構 39
圖4.1全系統電路架構圖 42
圖4.2時脈控制之栓鎖比較器及遲滯示意圖 44
圖4.3時脈控制之栓鎖比較器佈局 45
圖4.4 (a)七位元非同步骨牌二元搜尋控制迴路 (b)穩壓模式啟動電路 (c)電壓誤差偵測器 46
圖4.5 (a)骨牌二元搜尋之操作模式 (b)骨牌二元搜尋與傳統SAR之比較 47
圖4.6 (a)七位元非同步骨牌二元搜尋控制迴路與穩壓模式啟動電路佈局及(b)電壓誤差偵測器佈局 47
圖4.7 電壓誤差偵測器操作示意圖 49
圖4.8 六位元可調式非同步雙向控制迴路及操作流程 50
圖4.9 六位元可調式非同步雙向控制迴路佈局 51
圖4.10 PMOS電源陣列電路圖 53
圖4.11 PMOS電源陣列中M0之電路佈局 53
圖4.12 PMOS電源陣列之電路佈局 54
圖4.13 超低電壓快鎖式數位控制低壓降線性穩壓器架構圖 54
圖4.14 電路模擬之Bonding wire模型 56
圖4.15 電路佈局圖與示意圖 57
圖4.16 晶片微影圖 57
圖4.17 在TN90GUTM利用三級Inverter的環型震盪器做溫度對震盪頻率之模擬分析 58
圖4.18 Pre-layout Simulation (TT, 27°C, Load Current= 2.4mA-480uA-2.4mA ) 59
圖4.19 Pre-layout Simulation (FF, 75°C, Load Current= 2.4mA-480uA-2.4mA ) 59
圖4.20 Pre-layout Simulation (SS, 0°C, Load Current= 2.4mA-480uA-2.4mA ) 60
圖4.21 Post-layout Simulation(TT, 27°C, Load Current= 2.4mA-480uA-2.4mA ) 60
圖4.22 Post-layout Simulation(FF, 75°C, Load Current= 2.4mA-480uA-2.4mA ) 61
圖4.23 Post-layout Simulation(SS, 0°C, Load Current= 2.4mA-480uA-2.4mA ) 61
圖4.24 線性調節率(Line regulation)之模擬 62
圖4.25 負載調節率(Load regulation)之模擬 62
圖4.26 各製程與溫度變異下之靜態電流以及電壓追鎖時間 63
圖4.27 Asynchronous SAR在TT 27°C下的電壓追鎖情形 64
圖5.1量測儀器示意圖 66
圖5.2 負載電流2.4mA電壓追鎖量測結果 67
圖5.3 負載電流1.2mA電壓追鎖量測結果 67
圖5.4 負載電流480µA電壓追鎖量測結果 68
圖5.5 2.4mA到480µA負載轉換量測結果 68
圖5.6 負載電流2.4mA時之輸出電流 69
圖5.7 負載電流2.4mA時之輸入電流(IQ=4.7µA) 69

表目錄
表2.1線性穩壓器與切換式穩壓器之特性比較 11
表2.2 NMOS與PMOS功率電晶體之比較表 24
表3.1 文獻比較表 40
表4.1超低電壓數位控制低壓降線性穩壓器各特性之設計方法 43
表4.2預計規格表 55
表4.3 預計規格與模擬結果比較 64
表5.1佈局後模擬與量測結果比較表 66
表5.2 本篇論文提出之低壓降線性穩壓器與參考文獻之特性比較表 70

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