臺灣博碩士論文加值系統

本論文研究如何使用基於 ASAP7 PDK 的 7nm FinFET 技術提高標准單元設計的引腳可訪問性。我們設計了五個具有不同引腳佈局的六軌標准單元庫。第一個庫是通過使用商業佈局和佈線工具對底層單元庫進行基準測試，重新設計發現有引腳訪問問題的單元的引腳佈局而獲得的。第二個庫是通過為具有一些難以訪問的引腳的大型單行單元形成雙行高度單元而獲得的。第三個庫是通過採用 must-join 技術獲得的，該技術允許芯片級路由器完成雙行高度單元中內部網絡的一些不完整佈線。第四個庫是通過在具有引腳訪問困難的單元中的某處插入一些虛擬策略門獲得的。第五個庫是通過簡單地從單元庫中刪除具有引腳訪問困難的單元來獲得的。我們的研究發現前四個單元庫在解決引腳訪問問題上有自己的優勢，而第五個單元庫不是一個可行的解決方案。

This thesis studies how to improve pin accessibility of standard cell designs with a 7nm FinFET technology based on ASAP7 PDK. We design five six-track standard cell libraries with varying pin layouts. The first library is obtained by re-designing pin layouts of the cells found to have pin access problems through benchmarking the underlying cell library using a commercial placement and routing tool. The second library is obtained by forming double-row height cells for the large single-row cells which have some difficult-access pins. The third library is obtained by employing must-join technique that allows a chip-level router to complete some incomplete routing of internal nets in double-row height cells. The fourth library is obtained by inserting some dummy ploy gates somewhere in the cells with pin-access difficulty. The fifth library is obtained by simply removing the cells with pin access difficulty from the cell library. Our study finds out that the first four cell libraries have their own edges on addressing pin access problem while the fifth cell library is not a viable solution.

摘 要 iii
ABSTRACT iv
誌 謝 5
Content 6
List of Tables 7
List of Figures 7
Chapter 1. Introduction 8
1.1 Background 8
1.2 Scope of the Work and Contribution 9
1.3 Thesis Organization 10
Chapter 2. ASAP7 PDK and ASAP7L 10
2.1 ASAP7 PDK and ASAP7L 10
Chapter 3. Method and design 14
3.1 XPD6L_M 14
3.2 XPD6L_DR 15
3.3 XPD6L_DRM 19
3.4 XPD6L+ 22
3.5 XPD6L_Ex 22
Chapter 4. Experimental Results 23
4.1 Benchmark Circuits and Design Flow 23
4.2 Experimental Setup 24
4.2.1 Without Violations, test the core Utilization limits of each circuit 25
4.2.2 Power Stripe Planning 25
4.2.3 Two Ways of Pin Landing 26
4.3 Experiment results for each circuit 27
4.3.1 B19電路 27
4.4.1 Riscv電路 29
4.5.1 Neural Network電路 30
4.6.1 Aes電路 31
4.7.1 Gpu電路 32
Chapter 5. Conclusion and Future Works 32
References 33

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