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研究生:黃偉建
研究生(外文):WEI-JIAN HUANG
論文名稱:56Gb/四階脈衝振幅調變重定時器與三標記決策回饋等化器於四十奈米CMOS製程
論文名稱(外文):A 56Gb/s PAM-4 Retimer with a 3-tap Decision Feedback Equalizer in 40nm CMOS
指導教授:彭朋瑞
指導教授(外文):Pen-Jui Peng
口試委員:謝秉璇林鴻文
口試委員(外文):Ping-Hsuan HsiehHung-Wen Lin
口試日期:2021-01-13
學位類別:碩士
校院名稱:元智大學
系所名稱:電機工程學系甲組
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2021
畢業學年度:109
語文別:英文
論文頁數:65
中文關鍵詞:接收機四階脈衝振幅調變資料時脈回復電路
外文關鍵詞:ReceiverPAM-4CDR
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在近年來的有線通信標準中,已開始普遍使用四階脈衝振幅調變技術,使傳輸速度達到56Gb/s以上的高速傳輸。四階脈衝震幅調變相較於不歸零訊號有頻寬的優勢,但與不歸零訊號相比,在設計四階脈衝震幅調變接收器時,也會面臨額外的挑戰,由於在傳輸同樣速度的資料時,四階脈衝震幅調變,有四級的電平訊號,使得收發器會對通道損耗及反射更加敏感,在做符號檢測時必須提高電路判斷的準確度。

本論文提出一種採用四十奈米CMOS製程的二分之一速率低功耗四階脈衝調變接收器。該接收器的前端電路包括一個高補償多段可調整的線性等化器,分別對於低頻以及高頻進行補償,與多段可調的增益放大器,用來調整電路的增益,利於後面電路的運作,同時擁有三標記決策回饋等化器,補償更多的通道損耗與補償的精細度,成功將訊號解碼還原後,使用多工器將二分之一速率訊號合成全速率訊號輸出,能有效降低量測時的複雜度,在時脈方面,加入資料時脈回復電路增加整個系統的完整性。

接收機採用40nm CMOS 製程進行設計,晶片量測時採用放置於PCB板上(Chip On Board, COB)進行量測,56Gb/s四階脈衝震幅調變接收器各電路功能皆有正常運作,速率也達到預期目標56Gb/s,整體功耗為490.54mW,電源效率為9.08Pj/bit。

In recent years of wired communication standards, the fourth-order pulse amplitude modulation technology has been widely used, so that the transmission speed can reach high-speed transmission above 56Gb/s.
The front-end circuit of the receiver includes a high-compensation multi-stage adjustable linear equalizer to compensate for low frequency and high frequency respectively, and a multi-stage adjustable gain amplifier to adjust the gain of the circuit, which is beneficial to the operation of the subsequent circuit. It has a three-mark decision feedback equalizer to compensate for more channel loss and compensation precision. In the clock part, adding a data clock feedback circuit to increase the integrity of the entire system.
The receiver is designed with a 40nm CMOS process, and the chip is measured on the PCB (Chip On Board, COB). The circuit functions of the 56Gb/s fourth-order pulse amplitude modulation receiver are all operating normally. The rate has reached the expected target 56Gb/s. At 56Gb/s, the power consumption is 535.36mW and the power efficiency is 9.56Pj/bit.

Contents
書名頁
摘要
Abstract
誌謝
Contents
List of Figures
List of Tables
Chapter1 Introduction
1.1 Motivation
1.2 Previous work
Chapter2 Basic Theory
2.1 Transceiver Architecture
2.2 Continuous time linear equalizer
2.3 Decision Feedback Equalizer
2.4 Clock and data recovery (CDR)
2.4.1 Phase detector (PD)
2.4.2 Linear phase detector (Hogge PD)
2.4.3 Bang-bang phase detector (Alexander Phase Detector)
2.4.4 Charge pump
2.4.5 Loop filter
2.4.6 Loop stability analysis
2.4.7 JTRAN of Bang-bang CDRs
2.4.8 JTOL of Bang-bang CDRs
2.4.9 Driver
Chapter3 Design of the 56Gb/s PAM-4 Retimer
3.1 Overview
3.2 Receiver Building Blocks
3.2.1 Front-End
3.2.2 VGA
3.2.3 CTLE
3.2.4 Slicer
3.2.5 Decision Feedback Equalizer
3.2.6 Decoder(Thermometer to binary encoder)
3.2.7 1:2Demux
3.2.8 1:16 Demux
3.3 Transmitter Building Block
3.3.1 Coefficient Selector
3.3.2 Finite Impulse Response Circuit
3.3.3 2:1 Multiplexer Driver (Mux driver)
3.4 Clock Path
3.4.1 Poly Phase Filter
3.4.2 Phase Interpolator
3.4.3 Clock and Data Recovery
3.4.4 Design of digital CDR
Chapter4 Measurement
4.1 Measurement Set Up
4.2 Experimental Results
Chapter5 Conclusion and Future work
5.1 Conclusion
5.2 Future work
Chapter6 Reference

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