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研究生:許堯舜
研究生(外文):HSU YAO-SHUN
論文名稱:採用40奈米製程實現之用於軸承故障診斷的低功耗分層卷積神經網路硬體加速器
論文名稱(外文):A low-power hierarchical convolutional neural network hardware accelerator implemented in 40-nm CMOS technology for bearing fault diagnosis
指導教授:鍾菁哲
指導教授(外文):Chung Ching-Che
口試委員:李順裕盛鐸黃崇勛鍾菁哲
口試委員(外文):Lee Shuenn-Yuhsheng duoHuang Chung-HsunChung Ching-Che
口試日期:2022-07-06
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2022
畢業學年度:110
語文別:中文
論文頁數:92
中文關鍵詞:白高斯噪聲軸承故障診斷分層式卷積神經網路卷積神經網路低功耗晶片
外文關鍵詞:vibration signal analysisbearing fault diagnosishierarchical convolutional neural networkconvolutional neural networklow power
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現代科技的進步日新月異伴隨著生活品質的成長,近幾年的趨勢技術機器學習充斥在各行各業已經成為現今科技裡面不可或缺的角色。在很多工廠裡充斥著各種各樣的機台,例如:電動機,CNC工具機等不同的機械。這些機器在運行的過程中常常會有故障發生,早期只能以人工的方式或抓取一段大約的時間排除,不僅不準確且危險。而現在使用機器學習的方法進行智慧監控,把工具機或電動機產生的不正常數據行為進行機器學習的訓練萃取該故障數據的特徵,爾後透過在該機器的軸承實施實時監控即可實施預防性維護,不僅可以及早預防工廠的生產線因為機器故障停擺也可以預先防護操作員在操作工具機上的安全。
本論文使用分層式卷積神經網路的方式進行訓練,並以40nm CMOS製程實現。使用分層式卷積神經網路的優點為先將具有相似特徵或類別的圖像資料先分類再進行訓練,相較傳統卷積神經網路需要經過多層運算才能得到每次分類結果,經本實驗數據得知只需少量的運算即可判別並輸出結果且可以大幅的下降神經網路模型所需參數量以及達到辨識軸承故障數據95% 以上的準確度。
另外本論文亦使用加入白高斯雜訊的模擬數據,增加到訓練資料集以提升模型的準確度,以及測試此分層式卷積神經網路的抗噪效果,以因應工廠裡面各種不同發生雜訊的情況產生。各項數據結果均確認所提出之分層式卷積神經網路有良好的抗噪效果。
本論文在硬體實現的部分使用電源門控技術,將待機狀態的記憶體之電源關閉,達成低功耗的實現。本論文實現電路使用 TSMC 40nm CMOS 製程,在硬體描述階段,經過調整各階段所需bits數量的實驗結果後,所實現之硬體加速器判斷軸承健康的準確率達到95.31%。後續經由電路合成以及自動佈局繞線後各項數據表明,所提出之硬體電路工作頻率最高可達100MHz,此時功耗為65.608 mW.

The rapid progress of modern technology is accompanied by the growth of the quality of life. In recent years, the trend of technology machine learning is flooded with all walks of life and has become an indispensable role in today's technology. Many factories are filled with machines, such as electric motors, CNC machine tools, and other machinery. These machines often have faults during their operation. In the early days, they could only be eliminated manually or for a particular time, which was inaccurate and dangerous. Now, machine learning methods are used for intelligent monitoring, and the machine tools or the abnormal data behavior generated by the motor is trained by machine learning to extract the characteristics of the fault data. Then preventive maintenance can be implemented by real-time monitoring of the machine's bearing. The safety of the operator can be protected while operating the machine tool.
This thesis uses a hierarchical convolutional neural network for training and hardware implementation in TSMC 40nm CMOS technology. Although the advantage of the hierarchical convolutional neural network is to first classify image data with similar characteristics or categories, it is known from the experimental result that the number of parameters calculated by the neural network can be significantly reduced, and the accuracy of classifying bearing fault accuracy can reach more than 95%.
In addition, this thesis also uses the simulation data with white Gaussian noise added to the training dataset to improve the model's accuracy and test the anti-noise simulation of the cascaded neural network in response to various noise occurrences in the factory. All data results confirm that the proposed hierarchical convolutional neural network has a good anti-noise effect.
In this thesis, power gating technology is used in the hardware implementation to turn off the power of the memory in the standby state to achieve low power consumption. The circuit implemented in this work uses the TSMC 40nm CMOS process. In the hardware implementation, after adjusting for the number of bits required in each phase, the implemented hardware accelerator has an accuracy of 95.31%. The following simulation data after logic synthesis and automatic layout and routing show that the operating frequency of the proposed hardware design can reach 100 MHz, and the power consumption is 65.608 mW.

摘要 II
Abstract III
Content V
List of Figures VII
List of Tables X
Chapter 1 Introduction 1
1.1 Introduction to Bearing Fault datasets 1
1.2 Advantages of machine learning method for Bearing Fault Diagnosis 7
1.3 Introduction to Hierarchical convolutional neural networkTree and advantage 19
1.4 The impact of signal-to-noise ratio on bearing Fault datasets & model accuracy 26
1.5 Motivation 30
1.6 Thesis Organization 32
Chapter 2 Software Implementation 33
2.1 Architecture overview 33
2.2 Dataset Pre-processing 35
2.3 Implementation Hierarchical convolutional neural networkon software and analysis 37
2.4 The impact of adding noise to CWRU datasets and analysis 48
2.5 Shuffle SNR and CWRU original dataset to get higher accuracy 51
2.6 Software platform comparison. 57
Chapter 3 Hardware Implementation 59
3.1 Fixed-point weight and Batch normalization layer bits trade-off 59
3.2 2D HCNN Hardware Accelerator Architecture 62
3.3 Hardware Memory power gating method 67
3.4 HCNN Hardware Implementation Analysis 70
3.5 Summary 74
Chapter 4 Conclusion and Future Works 75
4.1 Conclusion 75
4.2 Future Work 76
Reference 78


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