臺灣博碩士論文加值系統

在高速印刷電路板(Printed Circuit Board，PCB)之電路中，訊號連通柱(Via)已普遍作為不同佈線層訊號與訊號佈線間互連之用。最常見(最低成本)的連通柱結構為通孔(Plating Through Hole Via，PTH)，此結構會因佈線(Routing)換層間有使用帶線結構互連，其訊號連通柱將留下開路殘段(Open Stub)，而連通柱殘段(Via Stub)往往會引發訊號完整性問題。
以往至今常見的相關研究多以頻域呈現居多，然其對時域數位波形之影響較少探討，一般可以透過電磁軟體模擬得知殘段長度對於走線阻抗、接收端眼圖和插入損耗(Insertion Loss)的影響結果，並藉以判斷印刷電路板(Printed Board Circuit, PCB)是否需進行Via背鑽，但往往不知殘段對於訊號的影響及其原理。
依據上述原因，本篇將針對訊號連通柱殘段對其時域反射波形(Time-domain Reflection，TDR)與時域透射波形(Time-domain Transmission，TDT)的影響做一分析與探討。以分析圖表來協助判斷該殘段效應對於訊號品質的傷害程度是否為系統設計可承受範圍，並以電壓透射與反射原理及阻抗不連續，說明殘段長度對時域波形造成的影響。論證出利用縮短殘段長度，控制其引發之步階波平坦處的寬度，降低殘段對訊號品質的破壞，歸納出殘段長度與上升時間的關係式，作為簡易設計準則參考。

In the circuits of high speed printed circuit board (PCB), signal via has been commonly used to make interconnection between trace and trace on various routing layers. The most common signal via structure is plating through hole via (PTH), but this structure will leave an open stub due to connecting with a stripline structure while changing routing layer, and via stub often induces signal integrity problem.
From the past to now, common related research is mostly presented in the frequency domain, but its influence on the time-domain digital waveform is seldom discussed. The impact of Via stub length on trace impedance/receiving end-eye diagram/ Insertion loss can be recognized through the electromagnetic software simulation that judging whether back-drill is required. Nevertheless, the correlation of via stub about signal integrity.
As above reason, this paper will analysis and investigate the influence of signal via stub on time-domain reflection and transmission waveform. Used the analysis charts to determine the damage level of the via stub effect to the signal quality whether within the acceptable range of the system design, and based on the principe of voltage transmission and reflection and impedance discontinuity to explained about the significant for stub length will impact the signal quality as time-domain waveform. This paper demonstrated that shorten the via stub length to controlling the width of the flat part about step wave which induced by the stub, reducing the damage to the signal quality caused by the stub, and summarizing the relationship between the stub and rise time, can be used as a reference for simple design criteria.

目錄
摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 簡介 1
1-1研究動機 1
1-2文獻回顧 2
1-3章節概要 2
1-4成果及貢獻 3
第二章 電性說明 4
2-1連通柱及連通柱殘段的介紹 4
2-1-1連通柱等效模型與電氣特性介紹 5
2-2傳輸線反射與透射關係 8
2-2-1反射與傳輸參數說明 8
2-2-2欠載傳輸線多次反射/過載傳輸線多次反射 10
2-2-2-1欠載傳輸線的多次反射 (under driven) 10
2-2-2-2過載傳輸線的多次反射 (over driven) 12
2-3連通柱殘段對於訊號完整性的影響說明 13
2-3-1連通柱殘段之頻域電性說明-1/4波長的共振頻率解析 13
2-4 TDR/TDT介紹 16
第三章 連通柱殘段對於時域反射及透射波形之模擬與分析 17
3-1連通柱殘段時域反射及透射波形的形成說明 17
3-2連通柱殘段的長度對於TDR及TDT波形的影響 34
3-3連通柱殘段的阻抗對於TDR及TDT波形的影響 37
3-4連通柱殘段的上升時間對於TDR及TDT波形的影響 39
第四章 連通柱殘段對訊號完整性的影響 41
4-1連通柱殘段的長度對於訊號的影響 41
4-1-1模擬結構描述 41
4-1-2模擬分析與探討 43
4-2連通柱殘段對訊號影響之理論驗證 45
第五章 結論 47
參考文獻 49

圖目錄

圖2-1 連通柱的類型 4
圖2-2 連通柱殘段與背鑽的示意圖 5
圖2-3 單根訊號連通柱開路殘段之等效模型 6
圖2-4 連通柱過孔參數介紹 7
圖2-5 反射與透射電壓示意圖 8
圖2-6 當入射訊號遇到不匹配負載時的反射 9
圖2-7(a) 當傳輸線終端阻抗匹配 9
圖2-7(b) 當傳輸線終端短路 9
圖2-7(c) 當傳輸線終端開路 9
圖2-8 計算Under driven在傳輸線多重反射電路 11
圖2-9 計算Under driven在傳輸線多重反射彈跳圖 11
圖2-10 計算Under driven在傳輸線多重反射波形 11
圖2-11 計算Over driven在傳輸線多重反射電路 12
圖2-12 計算Over driven在傳輸線多重反射彈跳圖 12
圖2-13 計算Over driven在傳輸線多重反射波形 12
圖2-14 連通柱殘段1/4波長共振訊號傳輸方向 13
圖2-15 駐波擺幅改變卻停滯不動的情況 14
圖2-16 PTH為例的連通柱殘段波形影響 14
圖3-1 連通柱殘段的無損等效電路模型 17
圖3-2 無損等效電路的Vs(TDR)波形 18
圖3-3 連通柱殘段的無損等效電路模型-當T=0.455ns時電壓波反射與透射狀況 19
圖3-4 遇到阻抗不連續面產生反射與透射波 19
圖3-5 連通柱殘段的無損等效電路模型-VA電壓波的反射狀況 20
圖3-6 透射波到達VA開路端波形 21
圖3-7 連通柱殘段的無損等效電路模型-當T=0.755ns時電壓波反射與透射狀況 22
圖3-8 VA開路端反射波遇不連續面產生反射與透射波 22
圖3-9 連通柱殘段的無損等效電路模型-當T=0.905ns時電壓波反射與透射狀況 23
圖3-10 反射波(ρ3)到達VA開路端波形 24
圖3-11 連通柱殘段的無損等效電路模型-當T=0.91ns時電壓波反射與透射狀況 25
圖3-12 遇不連續面的反射與透射波到達Vs與VB端 25
圖3-13 連通柱殘段的無損等效電路模型-當T=1.055ns時電壓波反射與透射狀況 26
圖3-14 遇到阻抗不連續面產生反射與透射波(T=1.055ns) 26
圖3-15 連通柱殘段的無損等效電路模型-當T=1.205ns時電壓波反射與透射狀況 27
圖3-16 反射波(ρ3)到達VA開路端波形(T= 1.205ns) 27
圖3-17 連通柱殘段的無損等效電路模型-當T=1.21ns時電壓波反射與透射狀況 28
圖3-18 遇不連續面的透射波到達Vs與VB端(T= 1.21ns) 28
圖3-19 連通柱殘段的無損等效電路模型(包含反射透射係數) 29
圖3-20 連通柱開路殘段VA位置的時域透射及反射圖電壓大小與時間說明 30
圖3-21 連通柱開路殘段Vs(TDR)位置的時域透射及反射圖電壓大小與時間說明 31
圖3-22 連通柱開路殘段VB(TDT)位置的時域透射以及反射圖電壓大小與時間說明 32
圖3-23 波形彈跳圖分析總表 33
圖3-24 改變殘段長度(TDStub)時的Vs(TDR)端之模擬結果 35
圖3-25 改變殘段長度(TDStub)時的VB(TDT)端之模擬結果 36
圖3-26 改變殘段阻抗(Zstub)時的Vs(TDR)端之模擬結果 37
圖3-27 改變殘段阻抗(Zstub)時的VB (TDT)端之模擬結果 38
圖3-28 改變輸入訊號的上升時間(Tr)時，Vs(TDR)端之模擬結果 39
圖3-29 改變輸入訊號的上升時間(Tr)時，VB (TDT)端之模擬結果 40
圖4-1 結構之上視圖 41
圖4-2 結構變化之側視圖 42
圖4-3 微帶線之疊構剖面圖 42
圖4-4 帶線之疊構剖面圖 42
圖4-5 Sdd11連通柱殘段反射損失模擬結果 43
圖4-6 Sdd21連通柱殘段穿透損失模擬結果 43
圖4-7 連通柱殘段TDR波形 44
圖4-8 連通柱殘段TDT波形 44
圖4-9 連通柱殘段步階的形成 45
圖4-10 TDstub與Tr之關係對TDR影響-呼應波形彈跳圖算式 46
圖4-11 TDstub與Tr之關係對TDT影響-呼應波形彈跳圖算式 46




表目錄
表4-1 Via結構尺寸 41
表4-2 參數變化表 42
表4-3 微帶線(Microstrip line)尺寸 42
表4-4 帶線(Strip line)尺寸 42

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