臺灣博碩士論文加值系統

本論文目標在於設計生醫應用之時域式類比至數位轉換器，在轉換的過程中會插入部分時域之轉換與應用，相較於傳統電壓量化至數位的方式能達到更好的性能以及更加省電之目的。
本次設計為了達到省電之目的，電路以SAR ADC架構做延伸，電路架構大致可分成：取樣保持電路、時域式比較器、CDAC、循序漸進式控制邏輯與數位斜波充放電及控制單元。首先電路在取樣階段時，取樣保持電路會取樣輸入訊號，進入轉換階段後，時域式比較器會將取樣到的輸入電壓轉換成輸入時間，並比較輸入時間之快慢給出對應的邏輯訊號，CDAC依照給出的邏輯訊號去做對應切換並做下一次之比較，直到完成前十位元之轉換；再者，數位斜波充放電與控制單元會依照最後一次比較結果搭配邏輯控制電路對輸入節點做數位斜波式的充放電，在這期間時域式比較器會一直去比較輸入端換成的時間差值直到輸出邏輯準位與第十次的比較結果不同，這期間數位斜波式的充放電的次數會被記錄下來並解碼，與前面十位元做整合後輸出。
本論文下線晶片使用 TSMC 0.18μm CMOS標準製程實現，整體晶片佈局面積含 I/O pads為1.163×1.013 mm2，操作電壓為1.0V與1.8V，解析度為14位元，20kHz之取樣頻率，訊號對雜訊與失真比(SINAD)為78.63dB，有效位元(ENOB)為12.77bits，Fom為14.3fJ/c-s，電路整體功率消耗為2uW。

he goal of this paper is to design a 14-bit time-domain analog-to-digital converter (TADC) for biomedical applications. Some part of the conversion will be processed in time-domain. Compared with many traditional methods that directly quantize the voltage to digital output, this methodology can achieve better performance and consume less power.

In order to reduce power consumption, the circuit is extended by the SAR ADC architecture. The circuit architecture can be roughly divided into: sample-and-hold circuit, time-domain comparator, CDAC, SAR control logic and digital ramp charge /discharge and control unit. First, when the circuit is in the sampling stage, the sample and hold circuit will sample the input signal, then circuit entering the conversion stage, the time-domain comparator will convert the sampled input voltage into input time, and compare the speed of the input time to give the corresponding logic signal to CDAC switching and do next compare until the conversion of the first ten bits is completed.

Then, the digital ramp charging/discharging and control unit will perform digital ramp charging/discharging on the input node according to the result of the 10th comparison.
During this period, the time domain comparator compare the difference of input node continuously until the result is different from the result of tenth comparison. At this time, the number of charge/discharge will be recorded and encoded, and finally output 14 bits.

The design is fabricated in a TSMC 0.18μm 1P6M CMOS process with a chip area of 1.163×1.013 mm2 including PADs. The sampling rate of the Time Domain ADC is 20k-S/s, the resolution is 14-bit, and the supply voltages are 1.0V/1.8V. The power consumption is 2uW, the effective number of bits is 12.77 bit and the FOM is 14.3 fJ/c-s by post-simulations.

目 錄
摘 要 I
Abstract II
誌 謝 IV
目 錄 V
圖目錄 VIII
表目錄 XI
第1章 緒論 1
1-1 介紹 1
1-2 動機 1
1-3 資料轉換形式 3
1-4 時域ADC之優勢 4
1-5 論文架構 5
第2章 類比至數位轉換器介紹 6
2-1 類比至數位轉換器效能衡量標準 7
2-1-1 解析度 7
2-1-2 取樣速度 7
2-1-3 偏移誤差與增益誤差 7
2-1-4 非線性誤差 8
2-1-5 量化雜訊 9
2-1-6 訊號雜訊比與訊號對雜訊與諧波比 10
2-1-7 無雜散動態範圍 11
2-1-8 有效位元數 12
2-1-9 品質因數 12
2-2 類比至數位轉換器架構選擇 13
第3章 時域式類比至數位轉換器架構 14
3-1 取樣保持電路 15
3-1-1 單一電晶體開關 16
3-1-2 互補式開關 18
3-1-3 靴帶式開關 20
3-1-4 雙倍電壓靴帶式開關 22
3-2 比較器 25
3-2-1 時域比較器 25
3-2-2 電壓至時間轉換器 26
3-2-3 電壓至時間轉換器雜訊 28
3-2-4 電壓至時間轉換器輸入偏移電壓 29
3-2-5 電壓至時間轉換器回踢雜訊 31
3-2-6 相位偵測器 33
3-3 數位類比轉換器 35
3-3-1 數位類比轉換器架構 35
3-3-2 數位類比轉換器電容陣列設計 38
3-3-3 數位類比轉換器控制邏輯 40
3-4 邏輯控制電路 41
3-4-1 Synchronous Clocks And Control Logic 41
3-5 數位斜波充放電與控制單元 42
3-5-1 電壓至時間轉換器考量 42
3-5-2 Current Starved Inverter-Based VTC 43
3-5-3 Slope-Based VTC 46
3-5-4 Digital Slope 50
3-5-5 Differential Type Digital Slope 52
3-6 參考電壓緩衝器 54
3-7 佈局技巧與考量 56
3-7-1 同重心佈局 56
3-7-2 Dummy Device 56
3-7-3 Shielding 57
3-7-4 整體佈局圖 58
第4章 電路模擬與量測 60
4-1 佈局前模擬 60
4-1-1 取樣開關模擬 61
4-1-2 時域比較器之電壓至時間轉換器模擬 63
4-1-3 時域比較器之電壓至時間轉換器轉換曲線模擬 64
4-1-4 時域比較器之雜訊模擬 66
4-1-5 整體時域式類比至數位轉換器前模擬 67
4-2 佈局後模擬 (Post-Simulation) 68
4-3 性能總結與前後模擬比較 70
4-4 量測方法 71
4-5 晶片效能比較 72
4-6 量測結果 73
第5章 76
5-1 結論 76
5-2 未來展望 77
參考文獻 78

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