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研究生:馬國峰
研究生(外文):Guo-Feng Ma
論文名稱:使用適應性部分修復技術以提升快閃記憶體的良率及可靠度
論文名稱(外文):Adaptive Partial Replacement Techniques for Yield and Reliability Enhancement of Flash Memories
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
口試委員:呂學坤王乃堅李進福黃樹林洪進華
口試委員(外文):Shyue-Kung LuNai-Jian WangJin-Fu LiShu-Lin HwangJin-Hua Hong
口試日期:2022-07-19
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2022
畢業學年度:110
語文別:中文
論文頁數:126
中文關鍵詞:快閃記憶體適應性部分修復技術良率可靠度
外文關鍵詞:Flash MemoryAdaptive Partial Replacement TechniqueYieldReliability
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快閃記憶體是目前最受歡迎的非揮發型記憶體之一,由於其擁有低功耗、高存取速度以及可擴充性等優勢,而被廣泛運用於消費性電子產品中的儲存元件,像是固態硬碟、電腦以及行動裝置。隨著製程進步,快閃記憶體也發展出多階儲存細胞以及三維的架構,以提升其儲存密度,但是同時也因製程微縮,而導致晶片在製造時,維持其良率變得更困難,另外,快閃記憶體因細胞間的可靠度容限縮小,而造成細胞的耐久度降低,使得其可靠度受影響。在過去,錯誤更正碼以及內建自我修復技術常用來解決些問題,不過,為了達到目標的快閃記憶體良率以及可靠度,往往需要透過增加檢查位元數或者備用元件數的方式保護快閃記憶體,然而,分布於快閃記憶體中的故障或錯誤通常不會是均勻的,上述技術都屬於均勻保護技術,因此,可能會出現消耗大量硬體成本來修復稀疏的故障或錯誤而造成不必要的硬體浪費以及效能的損失。
為了改善上述的問題,本篇論文利用快閃記憶體以字為單位循序存取資料的特性,我們提出以細粒度的備用元件修復的適應性部分修復技術,並結合過去所提出的修正餘度 (Correction Slack) 概念,在編碼字的修正餘度接近臨限值時,將編碼字中有錯誤的次編碼字修復以有效保護快閃記憶體,實現以低硬體成本和避免系統效能下降的方式,達到維持快閃記憶體良率以及可靠度的目的。另外,本篇技術依照修復特性的不同,進而提出兩種架構: 局部適應性部分修復技術與全域適應性部分修復技術。
本篇論文也實現所提技術的硬體電路,並針對 1 GB 快閃記憶體的修復率、良率、可靠度及硬體成本進行分析。實驗結果顯示,本篇技術搭配粗粒度內建自我修復技術於測試模式時,在平均瑕疵數目為 50 時,修復率可達 99.5 % 以上,且在原始良率為 0.85 時,有效良率可維持在 99.92 % 以上;本篇技術於正常模式時,且錯誤發生率為 10-9 /小時的情況下,在經過 76 萬小時的操作後仍可維持達 0.99 之可靠度。最後,本篇技術以幾乎可忽略不計的硬體成本下,使得良率及可靠度能夠有效提升。
Flash memory is currently one of the most popular non-volatile memories. Due to the advantages of low power consumption, high access speed and scalability, it is widely used in storage elements of consumer electronic products such as solid-state drives, computers, and mobile devices. With the rapid advances of process technologies, there are also multi-level cells and three-dimensional structures developed for increasing the storage density. However, the shrinkage of the feature size makes it difficult to maintain the yield during chip manufacturing. In addition, due to the narrowing of the reliability margins between flash memory cells, the endurance of the cells is also reduced. Therefore, the reliability of the flash memory is threatened. In the past, error correction codes (ECC) and built-in self-repair (BISR) techniques were used to solve these problems. However, in order to achieve the target yield and reliability, it is necessary to increase the number of check bits or spare elements to protect the flash memory. However, the distribution of faults or errors in the flash memory are usually not uniform. The above techniques are both uniform protection techniques. It may occur that a large amount of hardware cost are comsumed to repair sparse faults or errors. This will incur unnecessary waste of hardware and lower performance.
To cure the dilemma described above, this thesis takes advantage of the characteristics of flash memory to access data sequentially in the word level and proposes adaptive partial repair techniques with spare words, We combines the concept of correction slack proposed in the past. When the correction slack of a codeword is closed to the specified value, faulty sub-codewords in the codeword are replaced with spare words. The incurred hardware overhead thus is low and we can avoid system performance degradation. In addition, this thesis proposes two architectures according to the different repair characteristics: the local adaptive partial repair technique (LAPRT) and the global adaptive partial repair technique (GAPRT).
We have implemented the hardware circuits of the proposed adaptive partial repair technique, and analyzed the repair rate, yield, reliability, and hardware overhead for 1 GB flash memory. Experimental results show that if the proposed technique is integrated with the coarse-grained built-in self-repair technique (CGBISR) in the test mode and the average injected number of defects is 50, the repair rate can reach more than 99.5 %. If the original yield is 0.85, the effective yield can be maintained above 99.92 %. In normal mode and the failure rate is 10-9/hour, its reliability can still be higher than 0.99 after 760,000 hours of operations. Finally, the proposed techniques can effectively improve yield and reliability with almost negligible hardware cost.
致謝 I
摘要 II
Abstract IV
目錄 VI
圖目錄 XI
表目錄 XV
第一章 簡介 1
1.1 背景及動機 1
1.2 組織架構 7
第二章 快閃記憶體之基本介紹與應用 8
2.1 快閃記憶體細胞 8
2.1.1 快閃記憶體細胞之基本架構 8
2.1.2 快閃記憶體細胞之基本操作 9
2.1.2.1 寫入操作 9
2.1.2.2 讀取操作 10
2.1.2.3 清除操作 12
2.2 快閃記憶體之陣列架構 12
2.2.1 非及型快閃記憶體 12
2.2.2 非或型快閃記憶體 14
2.3 固態硬碟 15
2.3.1 固態硬碟架構 15
2.3.2 快閃記憶體轉換層 16
2.3.2.1 邏輯/實體位址映射 17
2.3.2.2 壞區塊管理 18
2.3.2.3 垃圾回收 19
2.3.2.4 損耗均衡 19
2.3.3 快閃記憶體晶片 20
2.3.3.1 快閃記憶體晶片之接腳介紹 20
2.3.3.2 快閃記憶體晶片之內部構造 22
2.3.3.3 快閃記憶體晶片之操作時序圖 23
第三章 快閃記憶體之測試與修復技術 25
3.1 功能性故障模型 25
3.1.1 常見記憶體之故障模型 25
3.1.2 快閃記憶體之特定故障模型 27
3.2 快閃記憶體之測試 29
3.2.1 測試流程 29
3.2.2 測試演算法 30
3.3 快閃記憶體之相關容錯技術 31
3.3.1 內建自我修復技術 31
3.3.1.1 內建自我測試 32
3.3.1.2 內建備用分析 34
3.3.2 錯誤更正碼 36
3.3.2.1 BCH碼 37
3.3.2.2 低密度奇偶檢查碼 38
3.3.3 故障避免技術 39
3.3.3.1 降低讀取干擾技術 39
3.3.3.2 降低資料保留錯誤技術 40
3.3.3.3 資料編碼技術 40
第四章 適應性部分修復技術 41
4.1 適應性部分修復技術基本概念 41
4.2 局部適應性部份修復技術 44
4.3 全域適應性部份修復技術 46
4.4 適應性部分修復演算法 47
4.5 適應性部分修復技術於測試模式時之操作流程與範例 51
4.5.1 內建自我測試及修復流程 53
4.5.2 內建自我測試及修復之範例 54
4.6 適應性部分修復技術於正常模式時之操作流程與範例 57
4.6.1 寫入操作流程 57
4.6.2 讀取操作流程 59
4.6.3 適應性部分修復技術之範例 60
4.7 適應性部分修復技術硬體架構 64
4.7.1 地址產生器模組 66
4.7.2 錯誤資訊產生器模組 67
4.7.3 錯誤資訊暫存器模組 68
4.7.4 適應性地址重映射模組 69
4.7.5 備用次編碼字及備用資訊內容定址記憶模組 70
4.7.6 控制器狀態圖 72
第五章 實驗結果 74
5.1 瑕疵分布與故障型態 74
5.2 修復率分析 75
5.3 良率分析 79
5.4 可靠度分析 85
5.5 硬體成本分析 91
5.6 效能損失分析 99
5.7 超大積體電路實現 101
第六章 結論與未來展望 103
6.1 結論 103
6.2 未來展望 103
參考文獻 104
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