臺灣博碩士論文加值系統

隨著科技的快速發展，電子產品不斷追求輕薄短小等趨勢，逐漸逼近摩爾定律的極限，而為了讓晶片的效能持續提升，後段封裝技術開始被重視，三維積體電路（3DIC）也隨之被發展出來。過去的3DIC多是利用矽穿孔（Through Silicon Via；TSV）達到垂直整合的結果，現今由於銅優異的物理特性，而發展出銅銅直接接合技術。銅銅接合前，需要通過化學機械研磨（CMP）使接合表面平坦化，越平坦的表面，其接合後介面的缺陷則越少，然而即使在現今的研磨技術下，銅表面仍無法達成原子級的平坦，意味著接合後的介面必定會有孔洞的產生，這些孔洞則會影響電子元件日後的可靠度以及性能。為了探究孔洞在接合介面中的演變，本實驗室過去曾利用表面粗化後的電鍍銅進行接合，並觀察接合後的孔洞形貌變化[1]，而(111)優選方向的奈米雙晶銅則由於其優異的性質，被發現可在150°C的低溫下完成接合[2]，因此本實驗將利用(111)優選方向的奈米雙晶銅與隨機晶面方向之電鍍銅進行接合，觀察其介面孔洞形貌的變化，並和過去的研究進行比較。

本實驗使用(111)平面奈米雙晶銅與隨機晶面方向之電鍍銅兩種試片，並利用溫度、時間、壓力以及有無進行蝕刻處理等四種參數進行接合，接合後透過聚焦離子束（FIB）觀察孔洞形貌，並將接合介面與孔洞量化以孔洞高度（Void height）、孔洞比例（Void fraction）以及接合比例（Bonding fraction）三種參數進行分析，在觀察後發現，擁有奈米雙晶銅之接合試片，在150°C較短的退火時間便可達到良好的接合結果，且當退火時間拉長到24小時，可觀察到明顯的表面擴散，而單純用電鍍銅進行接合的試片，在退火150°C 24小時後，才可成功接合。

With the rapid development of technology, electronic products were made even tinier and thinner. The size of the semiconductor has gradually approached the limit of Moore's Law. To continuously improve the performance of the chip, back-end packaging technology has been advanced and valued. The three-dimensional integrated circuit (3DIC) has also been generated. In the past, 3DIC was mostly used Through Silicon Via (TSV) to achieve the result of vertical integration. Nowadays, due to the excellent physical properties of copper, copper bonding technology has been developed. Before bonding copper, chemical mechanical polishing (CMP) is required to flatten the bonding surface. The flatter the surface, the fewer defects on the bonding interface would cause. However, even with today’s CMP technology, scientists are still unable to make the copper surface flatten as atomic level flatness, which means that the bonding interface will still have voids. These voids will influence the reliability and performance of the electronic components. To explore the evolution of voids on the bonding interface, we used to utilize electroplated copper with roughened surfaces to bond and then observing the transformation of voids on it. Due to the excellent properties of highly (111)-oriented nanotwinned copper (nt-Cu) was found being able to be bonded at a low temperature of 150°C, the experiment will use nt-Cu and randomly oriented electroplated copper for bonding. After then, the transformation of the voids will be observed and compared with the past studies.

This experiment will use two specimens which include nt-Cu and randomly oriented electroplated copper. The temperature, time, pressure, and etching treatment will all be the four parameters for bonding. After bonding, the focused ion beam (FIB) will be used to observe the transformation of the voids. The bonding interface and voids are quantified and analyzed by three parameters: Void height (VH), Void fraction (VF), and Bonding fraction (BF). After the observation, it is found that the bonding will achieve a better result with nt-Cu with a short annealing time at 150°C.

Moreover, when the annealing time is extended to 24 hours, surface diffusion becomes more obvious. On the contrary, the randomly oriented electroplated copper can only be successfully bonded after annealing at 150°C for 24 hours.

摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
第一章 緒論 1
1.1前言 1
1.2三維積體電路（3DIC）之進程與矽穿孔（TSV）技術 3
1.3 研究動機 7
第二章 文獻回顧 9
2.1 晶圓接合簡介 9
2.1.1晶圓接合歷史 9
2.1.2晶圓接合的種類 10
2.1.3影響晶圓接合之因素 12
2.2 銅銅接合簡介 15
2.2.1銅銅接合種類 15
2.2.2銅銅接合機制 17
第三章 實驗步驟與研究方法 19
3.1 實驗流程與目的 19
3.2 實驗試片製備 20
3.3 實驗試片前處理 22
3.4 實驗試片接合 23
3.5 實驗試片退火 24
3.6 實驗試片分析 25
第四章 結果與討論 26
4.1 實驗系統分類 26
4.2 實驗試片表面形貌 27
4.3 孔洞擴散機制及理論 34
4.4 WE FNt系統分析 36
4.4.1 200°C預接合與退火分析 36
4.4.2 150°C預接合與退火分析 41
4.4.3 孔洞量化分析 43
4.5 WE FNt系統與WE FE系統之比較 47
4.5.1 200°C預接合與退火分析 47
4.5.2 150°C預接合與退火分析 49
4.5.3影響孔洞差異之因素 50
4.5.4孔洞量化分析 52
4.6 WNt FE系統分析 54
4.6.1 200°C預接合與退火分析 54
4.6.2 150°C預接合與退火分析 57
4.6.3 孔洞量化分析 58
4.7 WNt FE系統與WE FE系統之比較 61
4.7.1 200°C預接合與退火分析 61
4.7.2 150°C預接合與退火分析 63
4.7.3 孔洞量化分析 64
4.8 WE FNt系統與WNt FE系統之比較 66
4.8.1 200°C預接合與退火分析 66
4.8.2 150°C預接合與退火分析 68
4.8.3 孔洞量化分析 69
4.9 孔洞演化理論 72
第五章 結論 75
參考文獻 77

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