臺灣博碩士論文加值系統

在我們前一批編號為UMOS-001的晶片，我們成功地藉由預先非晶化離子植入製程做出具有厚底氧化層的4H型碳化矽溝槽式閘極金氧半場效電晶體。然而，它的導通特 性以及耐壓表現皆不甚理想，導致對於晶片的分析也不夠全面。因此，在這篇論文中，我們調整了製程並製作了一批編號為UMOS-003的晶片，來提升元件性能並進一步分析元件特性。
我們發現，磷離子的預先非晶化植入製程除了能讓底部氧化層更厚之外，還會導致 臨界電壓的下降，也會降低元件的崩潰電壓。我們提出了提早崩潰的解釋，並以Sentaurus半導體元件與製程模擬軟體進行驗證。除此之外，我們也發現N+源極區域的光罩佈局會 影響到元件導通電流的大小。
藉由調整製程條件，我們成功地降低了元件的臨界電壓並讓元件的導通電流提升了2.5~3.7倍。此外，元件的崩潰電壓皆有被提升。溝槽式閘極金氧半場效電晶體的崩潰電壓可以達到1000伏特，而終端保護環測試結構的崩潰電壓則可以達到將近1200伏特。
不過，由於我們減少了多晶矽閘極的回蝕刻時間，在晶片平面以上有多晶矽的殘留，導 致在元件胞陣列中產生閘極-源極漏電流。閘極氧化層的厚度達140奈米，遠大於預期。 另外，對於1200伏特級的高功率元件來說，元件的崩潰電壓依舊未達標準。
由於在UMOS-003這批晶片中還有很多仍待解決的問題，我們對光罩佈局、實驗參數以及製程步驟都做了大幅度的調整以進一步優化元件的特性，並製作了編號為UMOS-004的晶片。
就光罩佈局的調整來說，我們在元件包陣列中採用了垂直式P型井接觸窗結構，因而設計了最小單位間距為4.1微米的元件。除此之外，我們調整了元件終端區的設計並 圓弧化金屬以及接觸窗的形狀，來提升元件的崩潰電壓。製程方面，我們調整預先非晶 化離子植入的條件，也首次增加了鋁離子的預先非晶化植入。閘極氧化層的製程條件則 是藉由實驗來進行調整。最後，我們提出解決多晶矽在晶片平面以上殘留問題的方法，該方法也可以簡化製作厚底氧化層的步驟。實際製作時，因為製程發生尚未釐清的意料之外的問題，使得閘極-源極漏電流問題依然存在，崩潰電壓比UMOS-003還低。所幸 終端結構的測試結構的耐壓可以達到1400伏特，可供1200伏特等級的功率元件使用。我們相信如果製程正常執行，本論文提出的各項改善，應該可以有效達成1200伏特等級的溝槽式閘極金氧半場效電晶體之特性目標。

In our previous lot named UMOS-001, we have successfully fabricated a 4H-SiC U- MOSFET with a thick bottom oxide (TBOX) through pre-amorphous ion implantation (PAI). However, both the on-state performance and the off-state performance are poor and thereby the analysis is not thorough. Therefore, in this thesis, we modified the process and fabricated a new lot named UMOS-003 to improve its performance and to further investigate its characteristics.
It is found that if the PAI is carried out with Ar implants and P implants, besides the TBOX thickness will become thicker, both the threshold voltage and the breakdown voltage will become lower. The mechanism of the early breakdown is proposed and verified using the Sentaurus Technology Computer-Aided Design (TCAD) simulator. Additionally, it is discovered that the different layout design of the N+ source region in the edge will influence the magnitude of the on current.
By modifying the process conditions, we successfully lowered the threshold voltage and increased the on current of the device. The on current is 2.5~3.7 times higher than that of
iii
UMOS-001. Besides, the breakdown voltages of both the UMOSFET cell array device and the guard ring test structure are raised. The breakdown voltage of the UMOSFET is beyond 1000 V and the breakdown voltage of the floating guard ring test structure is nearly 1200 V.
Nevertheless, since there are poly-Si residues remaining because of the reduced amount of poly-Si etching, the gate electrode and the source electrode is short together, which induces gate-to-source leakage current in the cell array device. The gate oxide thickness is about 140 nm, which is far thicker than expected. In addition, the breakdown voltage is still not high enough for the 1200 V class power MOSFETs.
As there are some unsolved problems remaining in UMOS-003, modifications in the layout design, the experimental parameters, and the fabrication process were made to further optimize the performance of the device. A lot named UMOS-004 was fabricated.
Regarding the layout design modifications, we introduced the orthogonal P-base contact structure in the cell array device and thereby designed the smallest cell pitch of the device to be 4.1 ????????m. Besides, we adjusted the junction termination structure and circularized the shape of the metal and the contact to raise the breakdown voltage. As for the process modifications, we altered the PAI condition and added a PAI condition: Ar+Al for the first time. Concerning the gate oxide conditions, short-loop experiments were performed to modify them. Last but not least, in order to solve the poly-Si residues problem, a simplified fabrication process of the TBOX structure was proposed. Unfortunately, during the fabrication processes, some abnormalities occurred. As a result, the problem of gate-to-source leakage current still exist and the breakdown voltage is even lower than that of UMOS-003. Luckily, the performance of the guard ring test structure is not affected and exhibit a breakdown voltage of nearly 1400 V, which can be used in the 1200 V class power MOSFETs. It is believed that if the fabrication processes run smoothly, the modifications we made will be effective to meet the standard of the 1200 V class UMOSFETs.

摘要 i
Abstract iii
誌謝 v
Contents vii
List of Tables ix
List of Figures x
Chapter 1 Introduction 1
1.1 Properties of 4H-SiC power devices 1
1.1.1 Higher breakdown voltage 1
1.1.2 Lower on-resistance 1
1.1.3 Lower reverse leakage current 3
1.1.4 Higher operation temperature 3
1.2 Development of vertical power MOSFETs 4
1.2.1 V-MOSFET structure 4
1.2.2 VD-MOSFET structure 5
1.2.3 U-MOSFET structure 5
1.3 Motivation 7
1.3.1 Poor on-state performance 8
1.3.2 Poor off-state performance 8
1.4 Thesis organization 9
Chapter 2 Performance Improvement 19
2.1 Process modification 19
2.1.1 Detailed process flow 20
2.2 Results and discussion 23
2.2.1 Device structure inspection 23
2.2.2 On-state performance 25
2.2.3 Off-state performance 29
Chapter 3 Further Modifications 54
3.1 Layout design modification 54
3.1.1 Main device 54
3.1.2 Single trench device 56
3.1.3 Test structure 57
3.2 Process modification 58
3.2.1 Split conditions 58
3.2.2 Experimental parameters 59
3.2.3 Detailed process flow 61
3.3 Results 64
Chapter 4 Summary and Future Work 93
4.1 Summary 93
4.2 Future work 94
References 96

[1] B. J. Baliga, Fundamentals of power semiconductor devices, 2nd ed. New York: Springer Science & Business Media, 2010.
[2] Y. Nanen, M. Kato, J. Suda, and T. Kimoto, “Effects of Nitridation on 4H-SiC MOSFETs Fabricated on Various Crystal Faces,” IEEE Transactions on Electron Devices, vol. 60, no. 3, pp. 1260-1262, 2013.
[3] A. A. Tamer, K. Rauch, and J. L. Moll, “Numerical Comparison of DMOS, VMOS, and UMOS Power Transistors,” IEEE Transactions on Electron Devices, vol. 30, no. 1, pp. 73-76, 1983.
[4] D. Ueda, H. Takagi, and G. Kano, “A New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance,” IEEE Transactions on Electron Devices, vol. ED-32, no. 1, pp. 2-6, 1985.
[5] R. A. Blanchard, “Method for making planar vertical channel DMOS structures,” U.S. Patent 4767722, 1986.
[6] S. Nakazawa, T. Okuda, J. Suda, T. Nakamura, and T. Kimoto, “Interface Properties of 4H-SiC (11-20) and (1-100) MOS Structures Annealed in NO,” IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 309-315, 2015.
[7] H. Yano, T. Hirao, T. Kimoto, H. Matsunami, K. Asano, and Y. Sugawara, “High Channel Mobility in Inversion Layers of 4H-SiC MOSFET’s by Utilizing (11-20) Face,” IEEE Transactions on Electron Devices, vol. 20, no. 12, pp. 611-613, 1999.
[8] S. M. Kong, H.J. Choi, B.T. Lee, S.Y. Han, and J.L. Lee, “Reactive Ion Etching of SiC Using C2F6/O2 Inductively Coupled Plasma,” Journal of Electronic Materials, vol. 31, no. 3, pp. 209-213, 2002.
[9] H. Cho, P. Leerungnawarat, D. C. Hays, S. J. Pearton, R. M. Strong, C. M. Zetterling, M. Östling, and F. Ren, “Ultradeep, low-damage dry etching of SiC,” Applied Physics Letters, vol. 76, issue 6, pp. 739-741, 2000.
[10] C. Han, Y. Zhang, Q. Song, Y. Zhang, X. Tang, F. Yang, and Y. Niu, “An Improved ICP Etching for Mesa-Terminated 4H-SiC p-i-n Diodes,” IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1223-1229, 2015.
[11] J. A. Cooper, Jr., “Structure for increasing the maximum voltage of silicon carbide power transistors,” U.S. Patent 6180958B1, 2001.
[12] Y. Li, J. A. Cooper, Jr., and M. A. Capano, “High-Voltage (3 kV) UMOSFETs in 4H-SiC,” IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 972-975, 2002.
[13] Q. Zhang, M. Gomez, C. Bui, and E. Hanna, “1600V 4H-SiC UMOSFETs with dual buffer layers,” in 2005 International Symposium on Power Semiconductor Devices and IC’s, 2005, pp. 211-214.
[14] T. Nakamura, Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. Sakairi, and Y.Yokotsuji, “High Performance SiC Trench Devices with Ultra-low Ron,” in 2011 International Electron Devices Meeting, 2011, pp. 26.5.1-26.5.3.
[15] S. Harada, M. Kato, T. Kojima, K. Ariyoshi, Y. Tanaka, and H. Okumura, “Determination of optimum structure of 4H-SiC Trench MOSFET,” in 2012 International Symposium on Power Semiconductor Devices and IC’s, 2012, pp. 253-256.
[16] D. Peters, R. Siemieniec, T. Aichinger, T. Basler, R. Esteve, W. Bergner, D. Kueck, “Performance and ruggedness of 1200V SiC — Trench — MOSFET,” in 2017 International Symposium on Power Semiconductor Devices and IC’s, 2017, pp. 239-242.
[17] Y. Wang, K. Tian, Y. Hao, C. Yu, and Y. Liu, “An Optimized Structure of 4H-SiC U-Shaped Trench Gate MOSFET,” IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2774-2778, 2015.
[18] Y. Wang, Y. Ma, Y. Hao, Y. Hu, G. Wang, and F. Cao, “Simulation Study of 4H-SiC UMOSFET Structure With p+-polySi/SiC Shielded Region,” IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3719-3724, 2017.
[19] Y. Z. Cheng, Y. Wang, X. Wu, and F. Cao, “4H-SiC UMOSFET With an Electric Field Modulation Region Below P-Body,” IEEE Transactions on Electron Devices, vol. 67, no. 8, pp. 3298-3303, 2020.
[20] J. Goh and K. Kim, “High Efficiency 1700V 4H-SiC UMOSFET with Local Floating Superjunction,” in 2020 International Conference on Electronics, 2020, pp. 1-5.
[21] K. Tian, A. Hallén, J. Qi, S. Ma, X. Fei, A. Zhang, and W. Liu, “An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss,” IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2307-2313, 2019.
[22] S. Harada, Y. Kobayashi, K. Ariyoshi, T. Kojima, J. Senzaki, Y. Tanaka, and H. Okumura, “3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field,” IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 314-316, 2016.
[23] F. T. Chien, Z. Z. Wang, C. L. Lin, T. K. Kang, C. W. Chen, and H. C. Chiu, “150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers,” Micromachines, vol. 11, no. 5, pp. 504, 2020.
[24] H. Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, and N. Soejima, “A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics,” in 2013 International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2013, pp. 43-46.
[25] A. Agarwal, K. Han, and B. J. Baliga, “Analysis of 1.2 kV 4H-SiC Trench-Gate MOSFETs with Thick Trench Bottom Oxide,” in 2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), 2018, pp. 125-129.
[26] V. Šimonka, A. Hössinger, J. Weinbub, and S. Selberherr, “Growth rates of dry thermal oxidation of 4H-silicon carbide,” Journal of Applied Physics, vol. 20, issue 13, 2016.
[27] A. Makhtaria, V. Raineric, F. La Via, G. Franzò, F. Frisina, and L. Calcagno, “Oxidation of ion implanted silicon carbide,” Materials Science in Semiconductor Processing, vol. 4, issue 4, pp. 345-349, 2001.
[28] Y. H. Tseng, C. Y. Lin, and B. Y. Tsui, “Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation,” IEEE Electron Device Letters, vol. 38, no. 6, pp. 798-801, 2017.
[29] M. Liu, S. Zhang, X. Yang, X. Chen, Z. Fan, X. Wang, F. Yang, C. Ma, and Z. He, “Enhancing oxidation rate of 4H–SiC by oxygen ion implantation,” Journal of Materials Science, vol. 54, pp. 1147-1152, 2018.
[30] Y. T. Shih, “Process and Characterization of 4H-SiC UMOSFET with Thick Bottom Oxide,” Master, Institute of Electronics, National Chiao Tung University, Hsinchu, 2020.
[31] “Sentaurus Technology Computer-Aided Design (TCAD) software L-2016.03,” see https://www.synopsys.com/silicon/tcad.html, 2010.
[32] Y. T. Lu, “A study on the Residual Defective Region After 4H-SiC Local Oxiation Process Using Ar Ion Implantation,” Master, Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, 2022.
[33] F. H. Lu, “A study on the 4H-SiC UMOSFET with a novel saddle P-base,” Master, Institute of Electronics, National Chiao Tung University, Hsinchu, 2021.
[34] J. Ziegler and J. Biersack, “SRIM-2013 software package,” see http://www.srim.org, 2013.