臺灣博碩士論文加值系統

本論文應用於序列通訊系統中的類比前端接收機，此接收機的傳輸速率為112GBit/sec，採用四階脈衝振幅調變(4-level Pulse-Amplitude Modulation，PAM4)進行傳輸，因此每個符元(Symbol)上編碼2個位元。由於訊號對頻寬的要求較高，通道的損失較大，因此利用連續時間線性等化器(Continuous-Time Linear Equalizer, CTLE)先將訊號進行頻率補償，再交由取樣電路(Sample-and-Hold, SAH)交錯輸出。之後使用後端的類比數位轉換器(Analog-to-Digital Converter, ADC)，將類比訊號轉換成數位訊號交給後續的數位電路處理，完成序列通訊系統的接收機類比電路(Analog Receiver)。
CTLE的架構主要由轉導放大器(Transconductance Amplifier, Gm)與轉阻放大器(Transimpedance Amplifier, TIA)組成。為了配合不同通道進行資料傳輸，因此在CTLE中，透過數位電路控制開關調整CTLE中電阻與電容值來調變增益補償量。SAH的架構採用自抬式開關(Bootstrapped Switch)的架構，可以擁有較佳的線性度，並利用多種補償方式得到更高的線性度。另外避免電路不匹配及製程偏移而造成類比前端輸出的共模電壓不相容ADC輸入共模電壓，因此加入共模回授電路(Common-Mode Feedback, CMFB)，利用負回授減少電路的不理想效應。
此設計採用台積電 28nm CMOS製程設計，使用的供給電壓為1.5V與1.2V，輸入訊號最大擺幅為+-400mV，輸入訊號最大頻寬為28GHz。在CTLE中，直流增益固定在4.5dB，28GHz的最大增益為19.5dB。我們定義峰值差(Peak Difference)為在28GHz時的增益扣除直流增益，並以1dB為單位調整達到9dB至15dB的峰值差。當中低頻補償在2dB，以100MHz為單位調整範圍從350MHz到1.05GHz。而SAH的信納比(Signal-to-(Noise+Distortion)-Ratio, SNDR)達到40dB以上。總消耗功率為185mW。

This thesis is applied to analog front-end receiver in serial-link communication system. The data rate is 112GBit/sec and the data is encoded with 4-level pulse-amplitude modulation (PAM-4), so each transmitting symbol contains 2 bits of information. Due to the higher requirements on the bandwidth and higher channel loss, the signal is compensated first by continuous-time linear equalizer (CTLE), then sent to sample-and-hold (SAH) to interleave the signal. After that, we use analog-to-digital converter (ADC) at back-end to convert analog signal to digital signal for digital circuit and complete analog receiver of the serial-link communication system.
The CTLE structure consists of transconductance amplifier (Gm) and transimpedance amplifier (TIA). In order to match different channels, resistors and capacitors of CTLE can be adjusted by the digital controller to change the compensation gain. The SAH structure adopts bootstrapped switch which has better linearity and obtains higher linearity by using many compensation methods. Moreover, to avoid output common-mode voltage of analog front-end is incompatible with the ADC input common-mode voltage which is caused by circuit mismatch and process offset, using common-mode feedback (CMFB) with negative feedback to reduce the impact of non-ideal circuit.
This design uses TSMC 28nm CMOS process and supply voltage are 1.5V and 1.2V. The maximum input swing is +-400mV and the maximum bandwidth of input signal is 28GHz. In the CTLE, DC gain is fixed 4.5dB and the maximum gain at 28GHz is 19.5dB. We define the peak difference as the gain at 28GHz minus the DC gain, and the tuning range is from 9dB to 15dB for each 1dB step. When the mid-frequency compensation is 2dB, the compensation can be adjusted in 100MH units to reach 350MHz to 1.05GHz. The SAH achieves 40dB signal-to-noise-plus-distortion ratio (SNDR). Total power consumption is 185mW.

摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
誌謝 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
圖目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
表目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
一、 緒論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 論文組織 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
二、 接收器鏈 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 接收器鏈介面 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 接收器鏈類比前端架構 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 接收器鏈等化器功能 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
三、 連續時間線性等化器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 架構 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 源極退化 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 高頻補償級 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 中低頻補償級 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 轉阻放大器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 共模回授電路 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 等化器輸出級 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
四、 取樣電路 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 傳統自抬式開關 (Conventional Bootstrapped Switch) . . . . . . . . . . . . . 27
4.3 雙路徑高速自抬式開關電路 (Dual-Path High-Speed Bootstrapped Switch) . . 29
4.4 取樣電路輸出級 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
五、 佈局與模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.1 佈局 (Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 模擬結果 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.1 頻率響應 (Frequency Response) . . . . . . . . . . . . . . . . . . . . . 38
5.2.2 回授穩定度 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2.3 快速傅立葉轉換 (Fast Fourier Transform, FFT) . . . . . . . . . . . . 43
5.2.4 大訊號模擬 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
六、 結論與未來展望 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
參考文獻 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
自傳 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

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