臺灣博碩士論文加值系統

為追求高傳輸速度，第五代通訊系統部分頻率推至毫米波頻段，而為同時向下兼容上代產品，射頻前端模組(RF Front-End Module, RF FEM)設計愈加複雜導致元件數與功率消耗激增，為有效延長電池壽命、增長待機時間，本篇論文針對寬頻、低功耗之低雜訊放大器(Low Noise Amplifier, LNA)進行研究。
本篇論文於第二章描述低雜訊放大器的基本原理與設計方法，包括常見的寬頻與低功耗技術回顧。第三章介紹台灣半導體研究中心(TSRI)所提供之高頻量測環境介紹，做為第四章晶片佈局規劃的參考依據，並對高頻探針校正技術(TRL)進行模擬。
第四章使用TSMC提供的0.18 μm CMOS製程實現低雜訊放大器設計，利用電晶體寄生電容(Cgd、Cgs)製造兩路並聯的RLC共振來達到較寬的阻抗頻寬，並利用降低電晶體偏壓與電流再利用(Current-Reused)技術來達到降低功耗的目標。

The 5th generation communication system are pushed to the millimeter wave frequencies in pursuit of high transmission speed. In order to be compatible with the previous generation products, the design of RF Front-End Module (RF FEM) has become complex, resulting in a surge in component count and power consumption. To extend the battery life and standby time, this thesis focuses on the research of low-noise amplifier (LNA) with broadband and low power consumption.
Chapter 2 introduces the basic principles and design methods of LNAs, including a review of common broadband and low-power technologies. Chapter 3 introduces the high-frequency measurement environment provided by Taiwan Semiconductor Research Institute (TSRI), which serves as the reference for chip layout planning in Chapter 4, and simulates the high-frequency probe calibration technology(TRL).
Chapter 4 uses the TSMC 0.18-μm CMOS process to realize the low-noise amplifier. By using transistor parasitic capacitances (Cgd、Cgs) to create two RLC impedance branches, the wideband impedance matching can be achieved. To reduce power consumption, the current-reused technology and lower transistor voltage is adopted in the design.

中文摘要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 前言 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 低雜訊放大器原理及設計 4
2.1 基本概念 4
2.1.1 雜訊源 5
2.1.2 雜訊指數 9
2.1.3 線性度 10
2.2 低雜訊放大器設計方法 12
2.2.1 設計流程 12
2.2.2 寬頻匹配技術 15
2.2.3 低功耗技術 18
第三章 量測系統介紹與佈局相關考量 21
3.1 高頻量測系統介紹 21
3.2 高頻量測系統的校正方法與流程 23
3.2.1 校正方法 23
3.2.2 水平校正 24
3.2.3 SOLT校正 25
3.2.4 TRL校正 27
3.3 佈局相關考量 29
3.3.1 PAD設計考量 29
3.3.2 被動元件佈局與特性考量 31
3.3.3 天線效應考量 33
第四章 晶片量測結果與討論 35
4.1 晶片實作一 35
4.1.1 電路架構 35
4.1.2 模擬與量測結果 38
4.1.3 結果討論與修正反模擬 40
4.2 晶片實作二 43
4.2.1 電路架構 43
4.2.2 模擬與量測結果 46
4.2.3 結果討論 49
第五章 結論 50
參考文獻 51

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