臺灣博碩士論文加值系統

摘要 i
ABSTRACT ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 3
1.3 論文架構 4
第二章 生醫電路介紹 5
2.1 生醫電路的困難挑戰 5
2.2 生醫電路的解決方法 7
第三章 類比前端電路 11
3.1 類比前端電路(Analog Front End, AFE)整體架構 11
3.2 類比前端放大器(Preamp) 13
3.2.1低雜訊放大器(LNA) 14
3.2.2可變增益放大器(VGA) 18
3.2.3低通濾波器(LPF) 21
3.3 類比數位轉換器(ADC) 24
3.3.1 逐次逼近類比數位轉換器(SAR ADC) 25
3.3.2 電容式數位類比轉換器(CDAC) 26
3.3.3 取樣開關(Sampling switch) 28
3.3.4 比較器(Comparator) 29
3.3.5 SAR邏輯(SAR Logic) 30
第四章 模擬與量測結果討論 32
4.1 模擬結果與討論 32
4.1.1 Preamp模擬結果 32
4.1.2 ADC模擬結果 35
4.1.3 AFE模擬結果 41
4.2 量測結果與討論 46
4.2.1 量測考量 47
4.2.2 量測結果 47
4.3 模擬與量測結果討論 63
第五章 結論與未來展望 65
5.1 結論 65
5.2 未來展望 66
參考文獻 67

[1] S.-Y. Lee et al., “A programmable implantable microstimulator SoC with wireless telemetry: application in closed-loop endocardial stimulation for cardiac pacemaker,” IEEE Trans. Biomed Circuits Syst., vol. 5, no. 6, pp. 511–522, 2011.
[2] T. Kugelstadt, Getting the Most Out of your Instrumentation Amplifier Design. Dallas: Texas Instrum. Inc., 2005.
[3] D. Han, Y. Zheng, R. Rajkumar, G. Dawe, and M. Je, “A 0.45 V 100-channel neural-recording IC with sub- W/channel consumption in 0.18 m CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 17–21, 2013, pp. 290–291.
[4] Q. Fan, F. Sebastiano, H. Huijsing, and K. A. A. Makinwa, “A 1.8uW 60nV capacitively-coupled chopper instrumentation amplifier in 65 nm CMOS for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 46, pp. 1534–1543, Jul. 2011.
[5] R. R. Harrison and C. Charles, “A low-power, low-noise CMOS amplifier for neural recording applications,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958–965, Jun. 2003.
[6] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, pp. 584–1614, Nov. 1996.
[7] E. M. Spinelli and M. A. Mayosky, “AC coupled three op-amp biopotential amplifier with active DC suppression,” IEEE Trans. Biomed. Eng., vol. 47, no. 12, pp. 1616–1619, Dec. 2000.
[8] C. Enz, E. Vittoz, and F. Krummenacher, “A CMOS chopper amplifier,” IEEE J. Solid-State Circuits, vol. 22, no. 3, pp. 335–342, Mar. 1987.
[9] Q. Fan, J. H. Huijsing, and K. Makinwa, “A 2.1 W area-efficient capacitively-coupled chopper instrumentation amplifier for ECG applications in 65 nm CMOS,” in Proc. ASSCC, 2010, pp. 337–340.
[10] B. B. Winter and J. G. Webster, “Driven-right-leg circuit design,” IEEE Trans. Biomed. Eng., vol. BME-30, pp. 62–66, Jan. 1983.
[11] E. M. Spinelli, N. H. Martinez, and M. A. Mayosky, “A transconductance driven-right-leg circuit,” IEEE Trans. Biomed. Eng., vol. 46, no. 12, pp. 1466–1470, Dec. 1999.
[12] J. Uehlin et al., “A bidirectional brain computer interface with 64-channel recording, resonant stimulation and artifact suppression in standard 65nm CMOS ,” in Proc. European Solid-State Circuits Conf., 2019, pp. 77-80.
[13] H. Chandrakumar and D. Markovic, “An 80-mVpp linear-input range, 1.6- G input impedance, low-power chopper amplifier for closed-loop neural recording that is tolerant to 650-mVpp common-mode interference,” IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2811–2828, Nov. 2017.
[14] Y. Tseng, Y. C. Ho, S. T. Kao, and C. C. Su, “A 0.09μW low power Front End biopotential amplifier for biosignal recording,” IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 5, pp. 508–516, Oct. 2012.
[15] S. Ha et al., “Integrated circuits and electrode interfaces for noninvasive physiological monitoring,” IEEE Trans. Biomed. Eng., vol. 61, no. 5, pp. 1522–1537, May 2014
[16] T. Tang, W. Goh, L. Yao and Y. Gao, “A 16-channel TDM analog frontend with enhanced system CMRR for wearable dry EEG recording,” in Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2017, pp. 33-36.
[17] O. Choksi and L. R. Carley, “Analysis of switched-capacitor common mode feedback circuit,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, pp. 906–917, Dec. 2003.
[18] M. Banu, J. M. Khoury, and Y. Tsividis, “Fully differential operational amplifiers with accurate output balancing,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 1410–1414, Dec. 1988.
[19] T. Kwan and K. Martin, “An adaptive analog continuous-time CMOS biquadratic filter,” IEEE J. Solid-State Circuits, vol. SC-26, pp. 859–867, June 1991.
[20] Yan Weixun, H. Zimmermann, "Continuous-Time Common-mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance," Workshop on Design and Diagnostics of Electronic Circuit and Systems, IEEE- DDECS 2008, vol., no., pp.1-5, April 2008.
[21] L. Luh, J. Choma, and J. Draper, “A continuous-time common-mode feedback circuit for high-impedance current-mode applications,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 363–369, Apr. 2000.
[22] R. H. Olsson, III, D. L. Buhl, A. M. Sirota, G. Buzsaki, and K. D. Wise, “Band-tunable and multiplexed integrated circuits for simultaneous recording and stimulation with microelectrode arrays,” IEEE Trans. Biomed. Eng., vol. 52, pp. 1303–1310, Jul. 2005.
[23] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
[24] G. Y. Huang, S. J. Chang, C. C. Liu, and Y. Z. Lin, “10-bit 30- MS/s SAR ADC using a switchback switching method,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 3, pp. 584–588, Mar. 2013.
[25] B. Razavi, “The bootstrapped switch [a circuit for all seasons],” IEEE Solid State Circuits Mag., vol. 7, no. 3, pp. 12–15, Sep. 2015.
[26] B. Razavi, “The StrongARM latch [a circuit for all seasons],” IEEE Solid-State Circuits Mag., vol. 7, no. 2, pp. 12–17, Jun. 2015.
[27] J. Xu, B. Busze, H. Kim, K. Makinwa, C. Van Hoof, and R. F. Yazicioglu, “A 60nV/Hz 15-channel digital active electrode system for portable biopotential signal acquisition,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2014, pp. 424–425.
[28] M. Altaf, C. Zhang, and J. Yoo, “A 16-channel patient-specific seizure onset and termination detection SoC with impedance-adaptive transcranial electrical stimulator,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2728–2740, Oct. 2015.
[29] B. G. Do Valle, S. S. Cash, and C. G. Sodini, “Low-power, 8-channel EEG recorder and seizure detector ASIC for a subdermal implantable system,” IEEE Trans. Biomed. Circuits Syst., vol. 10, no. 6, pp. 1058–1067, Apr. 2016.
[30] J. Xu et al., “A 665 μW silicon photomultiplier-based NIRS/EEG/EIT monitoring asic for wearable functional brain imaging,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 294–296, 2018.
[31] Tu, C.C.; Lin, T.H. “Measurement and parameter characterization of pseudo-resistor based CCIA for biomedical applications,” IEEE International symposium on Bioelectronics and Bioinformatics, Taiwan, 11-14 April 2014; pp. 1-4.
[32] L. Shen, N. Lu, and N. Sun, “A 1V 0.25µW inverter stacking amplifier with 1.07 noise efficiency factor,” IEEE J. Solid-State Circuits, vol. 53, no. 3, pp. 896–905, Mar. 2018.
[33] T.-Y. Wang et al., “A fully reconfigurable low-noise biopotential sensing amplifier with 1.96 noise efficiency factor,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 3, pp. 411–422, Jun. 2014.
[34] T. Ogawa, H. Kobayashi, M. Hotta, Y. Takahashi, H. San, and N. Takai, “SAR ADC algorithm with redundancy,” in Proc. IEEE Asia Pacific Conf. Circuits and Syst. (APCCAS), 2008, pp. 268–271.
[35] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176–177.
[36] J. Fredenburg and M. Flynn, “A 90 MS/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC,” in IEEE ISSCC Dig. Tech. Papers, 2012, pp. 468–469.