臺灣博碩士論文加值系統

摘 要 i
ABSTRACT ii
誌 謝 iii
Contents iv
Figure Captions vi
Table Captions vii
Chapter 1 Introduction of GaN HEMTs 1
1.1 Gallium Nitride (GaN) FETs 1
1.2 The Characteristics and issues of D-GaN HEMT 3
1.3 The Characteristics and issues of E-GaN HEMT 5
1.4 The Cascode D-GaN 7
1.5 The FP and MIS structure in the proposed D-GaN MIS-HEMT 8
1.6 Thesis Organization 9
Chapter 2 Prior Art and Design Goals 10
2.1 Shortcomings of Cascode D-GaN structure 10
2.1.1 Avalanche problem 10
2.1.2 Efficiency degradation 13
2.1.3 Reverse recovery 14
2.2 Issues of gate charge current control 15
2.3 Design Goals 16
2.3.1 Directly drive with Vth tracking technique 16
2.3.2 Proposed EMI Reduction and Fast Switching Techniques 17
Chapter 3 Proposed Anti-Conduction Control Technique 19
3.1 Architecture of Proposed Anti-Conduction Control Technique 19
3.2 Timing Diagram of the Anti-Conduction Control Technique 20
3.3 Low Offset Sense Amplifier 23
3.3.1 Architecture of the Low Offset Sense Amplifier 23
3.3.2 Sense Amplifier with Offset Cancellation 24
3.3.3 Comparator with Auto-Zeroing 25
3.4 The Accurate ULP UVLO 26
3.4.1 Architecture of the Accurate ULP UVLO 26
3.4.2 Timing diagram of the Accurate ULP UVLO 27
Chapter 4 Proposed EMI Reduction and Fast Switching Techniques 29
4.1 Miller Plateau Detector and Slew Rate Control 29
4.1.1 Slew rate control 30
4.1.2 Miller Plateau Detector 31
4.2 Inverting Buck-Boost Converter with ESFC 33
4.3 Fast Level Shifter 34
Chapter 5 Experimental Results 36
5.1 Chip Micrograph 36
5.2 Measured Vth tracking Process 37
5.3 Measured ESFC Operation and Switching Waveforms 38
5.4 Statistics of the Measurement Results 40
5.5 Comparisons with the Other GaN Driver Methodologies 42
Chapter 6 Conclusion and Future Work 44
6.1 Conclusion 44
6.2 Future Work 44
Reference 45

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