臺灣博碩士論文加值系統

本次設計了兩種不同電流控制模式的降壓轉換電路。提出的第一個轉換器採用新型的積分式電流感測電路並運用磁滯控制來縮短暫態響應時間，積分式電流感測可以提高整體轉換效率與減少功率上的消耗。第一顆晶片採用TSMC 0.18 um 1P6M，面積為1.107x 0.851〖mm〗^2，其輸入為3.3V，晶片輸出範圍由1V至2V，峰值效率在輸出為2V負載電流為300mA時得到90.6%。
第二顆提出的轉換器是採用自適應導通時間控制技術的仿DCR電流感測降壓轉換器。電路控制為自適應導通時間控制並以仿DCR電流感測電路以作為電流模式獲取電流訊號的調節器。晶片採用TSMC0.18um1P6M，面積為1.128x 0.91434 〖mm〗^2，其輸入範圍由3V至3.3V，晶片輸出範圍由1V至2V，峰值效率在輸出為2V負載電流為300mA時得到90.63%。

The thesis proposed two different current-sensing circuits and different controlled-mode buck converters. The first converter proposed uses a new integral current sensing circuit and uses hysteretic-controlled to acceleration transient response time. The integral current sensing can improve the overall conversion efficiency and reduce power consumption. The first chip uses TSMC 0.18 um 1P6M, with an area of 1.107x 0.851〖mm〗^2. It’s input is from 3.3V, and the chip output range is from 1V to 2V. The peak efficiency is 2V at the output and the load current is 90.6% is obtained at 300mA.
The second proposed buck converter is a pseudo-DCR current sensing buck converter with adaptive on-time control technology. The circuit control is adaptive on-time control and uses pseudo-DCR current sensing as a regulator for obtaining current signals in current mode. The chip adopts TSMC0.18um1P6M, the area is 1.128x 0.91434 〖mm〗^2, the input is from 3.3V, the peak efficiency is 2 at the output and the load current is 300mA obtained 90.63%.

摘要 i
ABSTRACT ii
致謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
1 第一章 緒論 1
1.1 研究背景與動機 1
1.2 動機與目的 3
1.3 文架構 3
2 第二章 降壓轉換器電路原理介紹 4
2.1.1 連續導通模式 6
2.1.2 非連續導通模式 10
2.2 降壓轉換器之電路控制模式介紹 13
2.2.1 脈波寬度調變 13
2.2.2 電壓模式控制 13
2.2.3 電流模式控制 15
2.2.4 磁滯模式控制 17
2.3 2.3 降壓轉換器之重要特性與定義 18
2.3.1 線性調節率 19
2.3.2 負載調節率 19
2.3.3 輸出電壓漣波 19
2.3.4 效率 20
2.3.5 暫態響應 21
2.3.6 暫態電壓 22
3 第三章 新型積分式電流感測技術之磁滯控制降壓式轉換器 23
3.1 架構介紹 23
3.1.1 新型積分式電流感測電路 26
3.1.2 動態斜率補償 28
3.1.3 磁滯控制電路 29
3.1.4 磁滯比較器電路 31
3.1.5 運算放大器 32
3.1.6 非重疊電路 33
3.1.7 驅動電路 34
3.2 電路模擬結果 34
3.3 晶片佈局圖與量測結果 38
3.3.1 晶片佈局 38
3.3.2 晶片腳位與定義 39
3.3.3 量測環境 40
3.3.4 量測結果 42
3.3.5 量測規格表與相關文獻 48
4 第四章 具有自適應導通時間控制技術的仿DCR電流感測降壓轉換器 50
4.1 架構介紹與原理分析 50
4.1.1 電流感測級(Current Sensing stage) 52
4.1.2 補償級(Compensator stage) 53
4.1.3 控制級(Control stage) 55
4.2 電路模擬結果 56
4.3 晶片佈局圖與量測結果 58
4.3.1 晶片佈局 58
4.3.2 晶片腳位與定義 59
4.3.3 量測環境 61
4.3.4 量測結果 62
4.3.5 規格表與其他文獻比較表 67
5 第五章 結論與未來展望 69
5.1 結論 69
5.2 未來展望 70
6 參考文獻 71

[1]R. W. E and D. M, Fundamentals of Power Electronics, MA, Norwell:Kluwer, Mar. 2007.
[2]K.H. Chen. Power Management Techniques for Integrated Circuit Design,2016.
[3]Garcerá, G., Figueres, E., & Mocholí, A. (2000). Novel three-controller average current mode control of DC-DC PWM converters with improved robustness and dynamic response. IEEE transactions on power electronics, 15(3), 516-528.
[4]T. Suntio, "Analysis and modeling of peak-current-mode controlled buck converter in DICM", IEEE Trans. Ind. Electron., vol. 48, pp. 127-135, Feb. 2001.
[5]P. J. Villegas, J. S, M. M. H, F. N, and J. Á. M, “Average current mode control of series-switching post-regulators used in power factor correctors,” IEEE Transactions on Power Electronics, vol.15, no.5, Sep. 2000.
[6]K. Leung et al., "Use of State Trajectory Prediction in Hysteresis Control for Achieving Fast Transient Response of the Buck Converter," Circuits and Systems, 2003. ISCAS apos;03. Proceedings of the 2003 International Symposium, vol. 3.
[7]P.-C. Lee, and H.-S. Chen et al., " Fast-transient DC–DC converter with hysteresis prediction voltage control," IET Power Electronics, Vol.10 no.3, Oct. 2017.
[8]K.C. Kuo, and L. Adrian "A linear MOS transconductor using source degeneration and adaptive biasing." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48.10 (2001): 937-943
[9]M. Nashed and A.-A .Fayed, “Current-Mode Hysteretic Buck Converter With Spur-Free Control for Variable Switching Noise Mitigation,” IEEE Trans. Power Electronics, vol. 33, no.1, pp. 650-664, Jan. 2018.
[10]莊永強，使用相位頻率鎖定技術之磁滯控制降壓轉換器與使用新式電流感測技術之脈波寬度調變降壓轉換器，國立臺北科技大學，電子工程系碩士班，碩士論文，臺北，2017。
[11]X. Qian and T. Teo, "A low-power comparator with programmable hysteresis level for blood pressure peak detection", Proc. TENCON, pp. 1-4, Jan. 2009.
[12]A. Yoo, M. Chang, O. Trescases, and N. Wai Tung, “High Performance Low-Voltage Power MOSFETs with Hybrid Waffle Layout Structure in a 0.25μm Standard CMOS Process,” Proc. of the 20th International Symposium on Power Semiconductor Devices and IC’s, pp. 95–98, May 18–22, 2008.
[13]J.-J. Chen, Y.-S. Hwang, Y. Ku, Y.-H. Li and J.-A. Chen, "A current-mode-hysteretic buck converter with constant-frequency-controlled and new active-current-sensing techniques", IEEE Trans. Power Electron., vol. 36, no. 3, pp. 3126-3134, Mar. 2021.
[14] W.-H. Yang, L. C. Chu, S. H. Yang, Y. J. Lai, S. Q. Chen, K. H. Chen, Y. H. Lin, S. R. Lin, and T. Y. Tsai, “An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) Devices,” IEEE International Solid-State Circuits Conference, pp. 126-128, Feb. 2018.
[15]H. Lei, and S. Luo, "Design considerations for small signal modeling of DC-DC converters using inductor DCR current sensing under time constants mismatch conditions." 2007 IEEE Power Electronics Specialists Conference. IEEE, 2007.
[16]K. Kuo and A. Leuciuc, "A linear MOS transconductor using source degeneration and adaptive biasing", IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 48, no. 10, pp. 937-943, Oct. 2001.
[17]Richtek, "Comparison of DCR Current Sense Topologies" Web site forhttps://www.richtek.com/Design%20Support/Technical%20Document/AN037
[18]Richtek, "Compensation Design for Peak Current-Mode Buck Converters" Web site for https://www.richtek.com/Design%20Support/Technical%20Document/AN028?sc_lang=en
[19]S.-W. Lee,” Demystifying Type II and Type III Compensators Using OpAmp and OTA for DC/DC Converters”, Texas InstrumentationApplication Report Power Management, SLVA662 – July 2022.
[20]C.-S. Huang, et al. "A fast-transient quasi-V 2 switching buck regulator using AOT control." IEEE Asian Solid-State Circuits Conference 2011. IEEE, 2011.
[21]C.-H. Tsai, Bo-Ming Chen, and Hsin-Lun Li. "Switching frequency stabilization techniques for adaptive on-time controlled buck converter with adaptive voltage positioning mechanism." IEEE Transactions on Power Electronics 31.1 (2015): 443.451.
[22] C.-S. Huang, et al. "A fast-transient quasi-V 2 switching buck regulator using AOT control." IEEE Asian Solid-State Circuits Conference 2011. IEEE, 2011.
[23] M.-D. Ker and C.-Y. Wu, “Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC’s,” IEEE Trans. Electron Devices, vol. 42, pp. 1297–1304, July 1995.
[24] M.-D. Ker and K.-C. Hsu, “Latchup-free ESD protection design with complementary substrate-triggered SCR devices,” IEEE J. Solid-State Circuits, vol. 38, no. 8, pp. 1380–1392, Aug. 2003.
[25]J.-J .Chen, et al. "A New Fast-Response Current-Mode Buck Converter With Improved I2-Controlled Techniques" IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol. 26, no. 5, pp. 903-911, May 2018
[26] W.-H. Yang, C.-J Huang, H.-H Huang, W.-T Lin, K.-H Chen, Y.-H Lin, S.-R Lin and T.-Y Tsai, "A Constant-on-Time Control DC–DC Buck Converter With the Pseudowave Tracking Technique for Regulation Accuracy and Load Transient Enhancement," IEEE Transactions on Power Electronics, vol. 33, no. 7, pp. 6187-6198, July 2018.
[27] M. Zhou, Z. Sun, Q. W. Low and L. Siek, "Multiloop Control for Fast Transient DC–DC Converter," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 219-228, Jan. 2019.
[28] W. Huang, L. Liu, X. Liao, C. Xu and Y. Li, " A 240-nA quiescent current 95.8% efficiency AOT-controlled buck converter with A 2 -comparator and sleep-time detector for IoT application ", IEEE Trans. Power Electron., vol. 36, no. 11, pp. 12898-12909, Nov. 2021.