臺灣博碩士論文加值系統

本論文提出了應用在3.1~10.6GHz的超寬頻低雜訊放大器(Ultra-Wide Band Low Noise Amplifier, UWB LNA)，使用台灣積體電路製造股份有限公司(TSMC)的0.18 μm CMOS製程技術。此電路的第一級是利用電阻回授方式的放大器架構，藉以達成寬頻的輸入阻抗匹配。第二級的部分為透過疊接(Cascade)兩個NMOS的共源級放大器，利用電流重複利用(Current Reused)的方式達到低消耗功率，並使用串聯尖峰電感的方式以增加頻寬完成寬頻增益。最後一級電路作為輸出級，使用源極隨耦器(Source follower)來完成50歐姆輸出阻抗匹配。本電路使用TSMC製程進行預模擬(Pre-simulation) ，電路操作在頻率3.1 GHz~10.6 GHz下，電路最大增益(Gain)+17.66 dB，輸入反射係數S11與輸出反射係數S22皆小於-10dB，最低雜訊指數為4.4 dB，功率消耗為11.2 mW。

This thesis presents the research and implement on low noise amplifier for wireless communication system. This paper proposes an ultra-wideband low noise amplifier used in 3.1~10.6 GHz, using TSMC 0.18 μm CMOS process technology.
The circuit uses current-reused technique from a three-stage amplifier. The first stage is the input stage, which uses the resistive feedback architecture to achieve wideband input matching. The second stage adopts current-reused cascaded common-source structure to lower the power consumption, and uses the shunt-series peaking inductor to obtain flat gain over a wide bandwidth. The last stage uses the output of the output buffer to achieve a 50 ohm matching. The circuit uses the TSMC process, and do a pre-simulation. The input reflection S11 and output reflection S22 are both less than -10 dB, the maximum gain is 17.66 dB, the minimum noise figure is 4.4 dB, and the power consumption is 11.2 mW.

摘要 i
ABSTRACT iii
目錄 v
表目錄 viii
圖目錄 ix
1 第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 2
2 第二章 低雜訊放大器介紹 4
2.1 低雜訊放大器簡介 4
2.2 低雜訊放大器設計考量 5
2.2.1 S參數(S parameter) 5
2.2.2 頻寬(Bandwidth) 6
2.2.3 雜訊(Noise) 7
2.2.4 穩定度(Stability) 11
2.2.5 線性效應(Linearity) 12
2.2.6 功耗(Power consumption) 15
2.3 常見低雜訊放大器架構簡介 15
2.3.1 電阻匹配式放大器(Resistive Termination) 16
2.3.2 電阻回授式放大器(Shunt Resistor Feedback) 17
2.3.3 1/gm匹配式放大器(1/gm Termination) 20
2.3.4 源極電感性退化放大器(Source Inductive Degeneration) 21
2.4 常見低雜訊放大器架構特性分析 22
3 第三章 超寬頻低雜訊放大器設計 23
3.1 電路簡介 23
3.2 輸入匹配級(Input matching stage) 24
3.3 電流重複利用電路架構 25
3.4 電流重複利用放大級(Current reused amplifier stage) 28
3.5 電流重複利用原理 30
3.6 緩衝器 33
3.7 輸出緩衝級(Output buffer stage) 35
4 第四章 模擬結果與結論 37
4.1 電路設計與考量 37
4.2 製程變異因素(Process corner) 37
4.3 電路模擬結果 39
4.3.1 Smith Chart 40
4.3.2 S參數(S parameter) 41
4.3.3 穩定度(Stability) 43
4.3.4 雜訊指數(Noise figure) 43
4.3.5 線性度(Linearity) 44
4.3.6 製程變異Fast/Fast corner模擬結果 45
4.3.7 製程變異Slow/Slow corner模擬結果 50
4.4 相關研究比較 55
4.5 結論 57
5 第五章 未來展望與討論 58
參考文獻 59

[1]曾智群，「應用於超寬頻之電容回授匹配與電流再利用之超寬頻低雜訊放大器」，碩士論文，國立交通大學電機學院研究所，2010。
[2]A. Bevilacqua and A. M. Niknejad, "An ultra-wideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers," IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2259-2268, Dec. 2004.
[3]F. Zhang and P. R. Kinget, "Low-power programmable gain CMOS distributed LNA," IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1333-1343, June 2006.
[4]Y. Yu, Y. E. Chen and D. Heo, "A 0.6-V low power UWB CMOS LNA," IEEE Microwave and Wireless Components Letters, vol. 17, no. 3, pp. 229-231, March 2007.
[5]K. Miyazaki, T. Morishita, K. Komoku and N. Itoh, "A current-reuse low-power LNA operated in moderate inversion region," in 2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 1-3, 2021.
[6]行動裝置的明珠，淺談射頻功率放大器。國家實驗研究院。檢自https://www.narlabs.org.tw/xcscience/cont?xsmsid=0I148638629329404252&sid=0J154561220884929254 (Jun. 26, 2022)
[7]呂學士編譯，本城何彥原著，「微波通訊半導體電路」，全華科技股份有限公司，2001。
[8]B.Razavi, RF Microelectronics, second edition, Prentice Hall, Inc., 2012.
[9]B. Johnson, “Thermal agitation of electricitv in conductors, ”Phys. Rev,, vol. 32, pp.97-109, Jul. 1928.
[10]H. Nyquist, “Thermal agitation of electricitv in conductors,” Phys. Rev., vol. 32, pp. 110-113, Jul. 1928.
[11]張益誠，「使用電流再利用架構設計3-16GHz超寬頻低雜訊放大器」，碩士論文，國立雲林科技大學電子與光電工程學系研究所，2012。
[12]徐瑋鴻，「CMOS 60 GHz寬頻低雜訊放大器及24GHz低雜訊放大器使用蜂巢型電感之設計」，碩士論文，國立成功大學電機工程學系研究所，2018。
[13]T. H. Lee., The Design of CMOS Radio-Frequency Intergrraated Circuit: Cambridge University Press, 1998.
[14]D. K. Shaeffer and T. H. Lee, "A 1.5-V, 1.5-GHz CMOS low noise amplifier," IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 745-759, May 1997.
[15]B. Razavi, Ran-Hong Yan and K. F. Lee, "Impact of distributed gate resistance on the performance of MOS devices," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 41, no. 11, pp. 750-754, Nov. 1994.
[16]D. M. Pozar, Microwave Engineering, third edition, John Wiley and Sons, Inc., 2005.
[17]林則孝，「串接式低雜訊放大器之增益平坦度與穩定度研究」，碩士論文，國立台北科技大學電資碩士班研究所，2014。
[18]Behzad Razavi, “Design of Analog CMOS Intergrated Circuits,” McGraw-Hill, 2000.
[19]陳煥能，「具抑制寬外增益功能之帶斥特性超寬頻低雜訊放大器與2.5-11 GHz主動式寬頻匹配超寬頻低雜訊放大器」，碩士論文，國立交通大學電信工程學系研究所，2006。
[20]Choong-Yul Cha and Sang-Gug Lee, "A low power, high gain LNA topology," in IEEE International Conference on Microwave and Millimeter Wave Technology Proccedings, pp. 420-423, 2000.
[21]H. Hsieh and L. Lu, "Design of ultra-low-voltage RF frontends with complementary current-reused architectures," IEEE Transactions on Microwave Theory and Techniques, vol. 55, pp. 1445-1458, July 2007.
[22]黃偉綸，「使用RC回授與基底偏壓技術設計超寬頻之低功耗雜訊放大器」，碩士論文，國立雲林科技大學電子工程系研究所，2014。
[23]T. -P. Wang, “Design and analysis of simultaneous wideband input/output matching technique for Ultra-Wideband Amplifier,” IEEE Access, vol. 9, pp. 46800-46809, 2021.
[24]Z. Zhang and L. Xu, “A X/Ku-Band broadband low noise amplifier in 0.18 μm CMOS,” in 2021 6th International Conference on Integrated Circuits and Microsystem(ICICM), 2021.
[25]D. Pang, Y. Gui, S. Wu, X. Wang and W. Gang, “An ultra-wideband low noise amplifier design in 0.13-μm CMOS Technology,” in 2021 IEEE International Conference on Intergrated Circuits, Technologies and Applications(ICTA), 2021.
[26]K. Joshi, M. K. Mandal and P. Mandal, “Design of a wideband differential LNA based in CMOS 180 nm Technology,” in 2021 IEEE MTT-S Interational Microwave and RF Conference(IMARC), 2021.