臺灣博碩士論文加值系統

近年來物聯網與人工智慧（AIOT）及5G產業的快速發展，使得行政管理、工業效率以及生活便利等方面進入嶄新時代；相關應用的產品中需要多樣化傳感器（Transducer）來接收各式各樣的訊號，而省電且高效率的類比數位轉換器（Analog-to-digital Converter, ADC）則為這些傳感器電路的核心。
為符合越來越高的應用複雜度，以及效能需求，傳統的ADC架構已經不敷使用，使得近年來許多研究採用了混合式的設計架構，混合多種傳統ADC，來擷取不同架構的優點用以互補；其中一種組合便是通過在DSM中結合低功耗SAR ADC作為多位量化器，可以實現同時兼顧高解析度、高動態範圍以及低功耗的要求，使得此種組合成為混合型ADC廣泛採用的架構。但在此類架構中，會使用到多個功能相似的DAC，而這些DAC通常由面積巨大的被動元件所組成；多餘的DAC會製造許多冗餘的面積消耗。因此本論文提出一種可應用在DSM混合SAR ADC架構中的類比電壓回授技術，使用硬體再利用特性，把多個相似的DAC合併為一個共用DAC，來達到節省面積的效果。
本論文以六位元二階離散時間(Discrete time, DT)DSM混合SAR ADC為系統架構，並採用UMC 0.18um CMOS製程，工作電壓為1.8V，應用於音頻信號，超取樣率64倍，來實現此技術。

In recent years, the rapid development of the AIOT and 5G industries has brought administrative management, industrial efficiency and convenience of life into a new era; Products for related applications require a variety of transducers to receive various signals, and high-efficiency analog-to-digital converters (ADCs) are at the heart of these transducers.
In order to meet the increasing application complexity and performance requirements, the traditional ADC architecture is no longer sufficient, so in recent years, many studies have adopted a hybrid design architecture, mixing a variety of traditional ADCs to capture the advantages of different architectures; one of the combinations is to combine the low-power SAR ADC in the DSM as a multi-bit quantizer, which can achieve the requirements of high resolution, high DR and low power consumption at the same time, making this combination a hybrid ADC widely adopted architecture. However, in this type of architecture, multiple DACs with similar functions are used, and these DACs are usually composed of passive components with large area; redundant DACs will create a lot of redundant area consumption. Therefore, this paper proposes an analog voltage feedback technology that can be applied in the DSM hybrid SAR ADC architecture. It uses the hardware reuse feature to combine multiple simil
ar DACs into a sharing DAC to achieve the effect of saving area.
This paper uses a 6-bit 2nd order discrete time (DT) DSM hybrid SAR ADC as the system architecture, and adopts UMC 0.18um CMOS process, 1.8V operating voltage, and 64 oversampling rate to implement this technology.

目錄
致謝 I
中文摘要..................................................................................................II
英文摘要................................................................................................III
目錄 IV
圖目錄 VIII
表目錄 XI
第1章 概論 1
1.1 研究背景與動機 1
1.2 論文架構 4
第2章 類比數位轉換器簡介 5
2.1 全幅範圍(FULL SCALE RANGE, FSR) 5
2.2 最大權重位元(MOST SIGNIFICANT BIT, MSB) 5
2.3 最小權重位元(LEAST SIGNIFICANT BIT, LSB) 5
2.4 量化誤差(QUANTIZATION ERROR) 5
2.5 量化器 7
2.6 奈奎斯特取樣定理 8
2.7 類比數位轉換器效能參數定義 9
2.7.1 解析度(Resolution) 9
2.7.2 信號雜訊比(SNR) 9
2.7.3 信號對雜訊和失真比(SNDR) 10
2.7.4 無雜散動態範圍(Spurious-Free Dynamic Range, SFDR) 10
2.7.5 有效位元(Effective Number of Bits, ENOB) 10
2.7.6 微分非線性(Differential Non-Linearity, DNL) 10
2.7.7 積分非線性(Integral Non-Linearity,INL) 12
第3章 類比數位轉換器架構 13
3.1 前言 13
3.2 奈奎斯特率類比數位轉換器架構 13
3.2.1 快閃式類比數位轉換器(Flash ADC) 13
3.2.2 逐次逼近暫存器式類比數位轉換器(SAR ADC) 15
3.2.3 管線式類比數位轉換(Pipeline ADC) 15
3.3 超取樣率類比數位轉換器三角積分調變器簡介 16
3.3.1 超取樣技術 18
3.3.2 雜訊移頻 19
3.3.2.1.一階之雜訊移頻 20
3.3.2.2.二階之雜訊移頻 23
3.3.3 三角積分調變器架構 24
3.3.3.1.單一迴路架構 24
3.3.3.2.多迴路架構 25
3.4 ADC架構的比較 26
3.5 近年ADC架構 27
第4章 系統設計與子電路模擬 29
4.1 系統架構 30
4.2 系統架構之模擬驗證 34
4.3 電路實現 36
4.3.1 控制時序產生電路 38
4.3.1.1.除頻器 (Freguency divider) 39
4.3.1.2.非重疊時脈產生器(Nonoverlapping) 39
4.3.1.3.模擬結果 40
4.3.2 積分器(Integrator) 42
4.3.2.1.交換式電容電路 44
4.3.2.2.運算放大器(Operation Amplifier ) 46
4.3.2.2.1.摺疊疊接式運算放大器 46
4.3.2.2.2.偏壓電路 47
4.3.2.2.3.共模迴授電路(Common-mode feedback, CMFB) 48
4.3.2.2.4.模擬結果 49
4.3.3 共用數位類比轉換器(Sharing DAC) 51
4.3.3.1.R2R Ladder DAC 51
4.3.3.2.電阻變異補償 52
4.3.3.3.參考電壓 54
4.3.3.4.輸出阻抗 54
4.3.3.5.輸入阻抗 56
4.3.3.6.二元權重開關補償 56
4.3.3.7.模擬結果 58
4.3.4 SAR量化器電路架構 59
4.3.4.1. 比較器 59
4.3.4.2.SAR邏輯電路(SAR Logic) 61
4.3.4.3.模擬結果 61
第5章 佈局與結果比較 64
5.1 模擬結果 64
5.2 模擬結果比較 67
5.3 量測考量 68
第6章 結論 70
6.1 結論與未來展望 70
參考文獻 72


圖目錄
圖1. 1智慧家庭 1
圖1. 2混合式DSM混合SAR量化器架構(a)傳統(b)本論文 3
圖2. 1量化誤差之機率密度函數分布....................................................6
圖2. 2 Mid-rise量化和量化誤差 7
圖2. 3 Mid-tread量化和量化誤差 8
圖2. 4奈奎斯特取樣率之頻譜 9
圖2. 5 2-bits DAC輸出範例 11
圖2. 6 DNL範例 11
圖2. 7 INL範例 12
圖3. 1 Flash ADC電路架構...................................................................14
圖3. 2 SAR ADC電路架構 15
圖3. 3 (a)Pipeline ADC電路架構(b)Stage內部架構 16
圖3. 4三角積分調變器區塊圖 17
圖3. 5三角積分調變器之架構 17
圖3. 6超取樣率轉換器之架構 18
圖3. 7經由低通濾波器後之功率頻譜密度 19
圖3. 8三角積分調變器之數學模型 20
圖3. 9一階之三角積分調變器架構 21
圖3. 10傳統二階三角積分調變器 23
圖3. 11一階及二階雜訊移頻之功率頻譜密度 24
圖3. 12 (a)CIFB (b)CIFF架構 25
圖3. 13 MASH架構 26
圖3. 14各ADC架構之應用範圍 27
圖3. 15 Zoom ADC架構圖 28
圖3. 16 DSM混合SAR量化器架構 28
圖4. 1 (a)傳統 (b)俱類比電壓回授技術 系統架構............................29
圖4. 2 PeakSNR-OSR Curve 31
圖4. 3系統極點(a)於單位元分布(b)造成的頻率響應 32
圖4. 4 DAC NTF Magnitude Response 34
圖4. 5 Simulink 系統模型 35
圖4. 6 Matlab模擬功率頻譜 35
圖4. 7 動態範圍模擬 36
圖4. 8混合型類比數位轉換器電路 37
圖4. 9系統時序控制 38
圖4. 10除頻器電路 39
圖4. 11非重疊時脈產生器電路 40
圖4. 12非重疊時脈 40
圖4. 13除頻器模擬結果 41
圖4. 14積分器電路 43
圖4. 15積分器操作狀態 (a)ψ1 (b)ψ2 44
圖4. 16互補式開關電路 45
圖4. 17摺疊疊接式運算放大器 47
圖4. 18高擺幅偏壓電路 48
圖4. 19交換式電容共模迴授電路 49
圖4. 20放大器模擬結果(波德圖) 49
圖4. 21 R2R Ladder DAC回授路徑 52
圖4. 22 R2R Ladder DAC電路圖 52
圖4. 23各種組合線性度 (a)6B+1T (b)5B+3T (c)4B+7T 53
圖4. 24 4B+7T R2R Segmented-Ladder DAC 55
圖4. 25輸入阻抗與輸入碼關係圖 56
圖4. 26二元權重開關補償 57
圖4. 27 共用DAC線性度模擬結果 58
圖4. 28 SAR量化器架構圖 59
圖4. 29 (a)動態比較器(b)SR Latch 60
圖4. 30位移式暫存器電路 61
圖4. 31比較器遲滯圖 62
圖4. 32 SAR量化器模擬結果(頻譜圖) 63
圖5. 1全電路佈局圖.............................................................................64
圖5. 2全電路佈局圖 65
圖5. 3完整電路Post-sim模擬結果之頻譜圖(TT_25°) 65
圖5. 4功耗分布 66
圖5. 5量測環境之設定 68
圖5. 6濾波電路及偏壓電路(a)Filter tank(b)LM317(c)OP27 69

表目錄
表 3.1各類ADC特性比較表 26
表 4.1系統規格 35
表 4.2各相位執行動作 38
表 4.3控制時序產生電路前模擬 41
表 4.4控制時序產生電路後模擬 42
表 4.5放大器規格 46
表 4.6第一級放大器前模擬 50
表 4.7第二級放大器前模擬 50
表 4.8第一級放大器後模擬 50
表 4.9第二級放大器後模擬 51
表 4.10共用DAC前模擬 58
表 4.11共用DAC後模擬 58
表 4.12比較器前模擬 62
表 4.13比較器後模擬 62
表 4.14 SAR量化器前模擬 63
表 4.15 SAR量化器後模擬 63
表5. 1 全電路Pre-sim模擬結果..........................................................66
表5. 2 全電路Post-sim模擬結果 66
表5. 3 模擬結果比較表 67

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