跳到主要內容

臺灣博碩士論文加值系統

(44.201.97.0) 您好!臺灣時間:2024/04/15 10:52
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:蕭宇鋒
研究生(外文):Hsiao, Yu-Feng
論文名稱:應用於系統級封裝之非破壞性高頻特徵電氣故障分析技術
論文名稱(外文):A Non-Destructive RF Signature Measurement Technology for System in Package Electrical Failure Analysis
指導教授:楊博惠
指導教授(外文):Yang, Po-Hui
口試委員:黃崇勛吳松茂
口試委員(外文):Huang, Chung-HsunWu, Sung-Mao
口試日期:2022-08-12
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2022
畢業學年度:110
語文別:中文
論文頁數:132
中文關鍵詞:SiP 封裝史密斯圖非破壞性故障分析向量網路分析儀
外文關鍵詞:SiP packagesmith chartnon-destructive failure analysisvector network analyzer
相關次數:
  • 被引用被引用:0
  • 點閱點閱:173
  • 評分評分:
  • 下載下載:22
  • 收藏至我的研究室書目清單書目收藏:0
現今的 3C 產品因應人們的需求,發展出更多功能、更低功耗、更高速和更小的體積,促使晶片製程和封裝工藝方面不斷的進步,因此越來越精密的走線和封裝技術讓產品在出現問題時,要找出故障點的難度大幅的提升,使得傳統的故障分析技術逐漸的不再適用。因此要如何精準快速的對封裝體進行電氣特性分析已經成為當前晶片封裝廠的重要議題。

傳統的 IC 封裝故障分析技術分為破壞性和非破壞性兩種方式;使用破壞性的技術時需要拆解封裝體進行分析,在這過程中難以保證原本內部的線路不受到損壞,導致額外非預期的故障;而當前最多使用的非破壞性技術為時域反射法(Time Domain Reflectometry, TDR),此技術在故障檢測上需要足夠的訊號反應時間,當製程精細到小於訊號的反應時間時將導致故障分析上的困難。因此為了解決時域訊號在先進製程中檢測的問題,並且在無需破壞封裝體的情況下快速分析故障,發展出了高頻的故障分析技術,使用向量網路分析儀(Vector Network Analyzers, VNA)量測待測物的頻域訊號進行分析。

本論文針對電路的頻率響應做進一步的探討,由文獻[28]得知,不同 IC 的各個接腳在 100 kHz - 200 MHz 頻率範圍下能夠產生相異的阻抗特徵,藉由正常和異常封裝產生不同的史密斯圖成功判斷 IC 封裝是否異常,但是現今封裝和 IC 的尺寸不斷縮小且 IC 中的晶片逐漸增加,200 MHz 的頻率需要再進一步提升,因此為了快速直觀的檢測先進製程的故障點,不僅找出異常的 IC 封裝,更能夠清楚的檢測故障位置和故障特性,並且分辨為封裝不良導致故障或晶片本身在生產時就
出現問題,我們在兩顆晶片並聯的 SiP 基板中晶片未通電的情況下量測各個接腳的電氣特性,提出了應用於系統級封裝的高頻阻抗特徵進行非破壞性的電氣故障分析,若檢測出異常,代表封裝有故障,反之則是晶片生產時出現問題;由於 IC封裝中每個接腳的電氣特性都不相同,且連接不同晶片對線路的電氣特性有很大的改變,因此在不同的頻寬下會產生不同的阻抗特徵,轉換成史密斯圖後能明顯比對出正常 IC 封裝和異常 IC 封裝的差異,為了證實我們提出的理論,本論文設計了一系列模擬球柵陣列(Ball Grid Array, BGA)的 IC 封裝基板,有意設計無故障的正常 IC 封裝樣本和各種已知故障的異常 IC 封裝樣本進行史密斯圖的量測和比對,然而在高頻的情況下進行手動的垂直接觸量測將導致不穩定的校正並且產生很大的誤差,因此設計了一組垂直滑動的探針機台固定量測時的壓力和角度,解決手動量測造成的手抖、壓力不一致和無法垂直的問題,最後在各個樣本的量測比對下,成功證實 1 MHz - 3 GHz 的頻率範圍下可以有效地辨別異常 IC 封裝發生的故障問題。
In response to people’s needs, today’s 3C products have developed more functions,lower power consumption, higher speed and smaller size, prompting continuous progress in chip manufacturing and packaging technology, so more and more sophisticated wiring and packaging technology. When there is a problem with the product, the difficulty of finding the failure point has been greatly improved, so that the traditional failure analysis technology is gradually no longer applicable. Therefore, how to accurately and quickly analyze the electrical characteristics of the package has become an important topic of the
current chip packaging factory.

The traditional IC packaging failure analysis technology is divided into two methods: destructive and non-destructive. When using destructive technology, it is necessary to disassemble the package for analysis. In this process, it is difficult to ensure that the original internal circuit is not damaged, resulting in additional unexpected failure. The most commonly used non-destructive technology is time domain reflectometry (TDR), which requires sufficient signal response time for failure detection. When the process is fine enough to be less than the signal response time, it will cause difficulties in failure analysis. Therefore, in order to solve the problem of detecting failures in advanced manufacturing processes with time-domain signals, and to quickly analyze failures without destroying the package, a high-frequency failure analysis technology has been developed. It uses a vector network analyzer (VNA) to measure the frequency domain signal of the device under test for analysis.

This paper further discusses the frequency response of the circuit. it is known from the literature [27] that the pins of different ICs can produce different impedance characteristics in the frequency range of 100 kHz - 200 MHz, which are generated by normal and abnormal packaging. Different smith charts have successfully judged whether the IC package is abnormal. however, the size of the package and IC is constantly shrinking and the number of chips in the IC is gradually increasing. The frequency of 200 MHz needs to be further increased. Therefore, in order to quickly and intuitively detect the failure point of the advanced process, not only to find out the abnormal IC package, we can more clearly detect the failure location and failure characteristics, and distinguish
whether the failure is caused by poor packaging or the chip itself has problems during production, we measure the electrical characteristics of each pin when the chip is not powered on in the substrate of two chips, and propose a high-frequency impedance characteristic applied to the System in Package for non-destructive electrical failure analysis. If an abnormality is detected, it means that the package is faulty, otherwise it is a problem during chip production; because the electrical characteristics of each pin in the IC package are different, and the electrical characteristics of the lines connected to different chips are greatly changed, so different impedance characteristics will be produced at different bandwidths. After converting to smith chart, the difference between normal IC package and abnormal IC package can be clearly compared. In order to confirm our theory, this paper designs a series of IC package substrates in ball grid array, and deliberately designs normal IC package samples without failure and abnormal IC package samples with various known failures for smith chart measurement and comparison, but manual vertical
contact measurements are made at high frequencies. It will lead to unstable calibration, resulting in larger errors. Therefore, a set of vertically sliding probe station is designed to fix the pressure and angle during the measurement process, so as to solve the problems of trembling hands, inconsistent pressure and inability to be vertical caused by manual measurement. Finally, through the measurement and comparison of each sample, it is successfully confirmed that the failure of abnormal IC package can be effectively identified in the frequency range of 1 MHz – 3 GHz.
摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
誌謝 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
表目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
圖目錄 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
第一章 緒論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 研究動機與目的 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 研究方法 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 研究流程 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 論文架構 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
第二章 非破壞性故障檢測技術 . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 物理特性故障檢測 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 光激發電子顯微鏡 . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 掃描電子顯微鏡 . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3 超音波掃描顯微鏡 . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.4 物理特性檢測整合分析 . . . . . . . . . . . . . . . . . . . . . . 13
2.2 電氣特性故障檢測 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 熱輻射顯微鏡 . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 類比特徵分析法 . . . . . . . . . . . . . . . . . . . . . . . . . . 15
vi
2.2.3 時間區域反射法 . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.4 電氣特性檢測整合分析 . . . . . . . . . . . . . . . . . . . . . . 24
第三章 高頻網路分析技術 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 網路特性參數量測 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 史密斯圖 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 傳輸線理論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 傳輸線模擬 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 網路分析儀簡介 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.6 網路分析儀原理 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.7 校正技術 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
第四章 量測技術實現 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 量測平台架設 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.1 BGA 封裝樣本 . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.2 校正板 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1.3 探針機台 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 高頻阻抗量測 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.1 雙層封裝基板樣本 . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.2 四層封裝基板樣本 . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 四層黏晶封裝基板樣本 . . . . . . . . . . . . . . . . . . . . . . 67
4.2.4 SiP 基板樣本 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.3 高頻特徵比對分析 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
vii
4.3.1 分析方法 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.3.2 SiP 樣本數值分析結果 . . . . . . . . . . . . . . . . . . . . . . 86
4.3.3 數值再驗性 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.4 高頻故障分析圖形化介面 . . . . . . . . . . . . . . . . . . . . 107
第五章 結論 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
參考文獻 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
[1] H. Wu, Y. Liang, W. Du, S. He, Y. Wang, and D. Lei, “Study of silver alloy wire decapsulation methods for failure analysis,” in Proc. IEEE 24th IPFA, Jul. 2017, pp.1-4.
[2] J. Tang, H. Ye, J. B. J. Schelen, and C. I. M. Beenakker, “Plasma decapsulation of plastic IC packages with copper wire bonds for failure analysis,” in Proc. IEEE 12th International Conference on Electronic Packaging Technology and High Density Packaging, Aug. 2011, pp. 1-5.
[3] C. H. Chu, Y. T. Lin, W. J. Hsu, C. T. Chang, P. S. Kuo, and Y. F. Hsieh, “Applying novel non-destructive failure analysis techniques on the package related failures,” inProc. IEEE 17th ICEPT, Aug. 2016, pp. 1391-1395.
[4] Q. Zhang, Y. Che, J. Li, and B. Liu, “BGA packaged IC sample preparing for electrical failure analysis,” in Proc. IEEE 23rd IPFA, Jul. 2016, pp. 116-119.
[5] J. H. Lagar, R. A. Sia, and M. C. Grancapal, “Non-destructive techniques for internal solder bump inspection of chip scale package-ball grid array package,” in Proc. IEEE 21th IPFA, Jun. 2014, pp. 362-365.
[6] M. Cason and R. Estrada, “Application of X-Ray MicroCT for non-destructive failure analysis and package construction characterization,” in Proc. IEEE 18th IPFA, Jul. 2011, pp. 1-6.
[7] B. MR and B. VJ, “ABCs of Photo Emission Microscopy,” Electronic Device Failure Analysis Magazine, vol. 5, pp. 13-20, 2003.
[8] R. J. Anstead, “Failure Analysis using a Scanning Electron Microscope,” in Proc. IEEE 6th Annual Reliability Physics Symposium, Nov. 1967, pp. 127-137.
[9] Y. Ju, M. Saka, and H. Abe, “NDI of delamination in IC packages using millimeterwaves,” IEEE Trans. Instrum. Meas., vol. 50, no. 4, pp. 1019-1023, Aug. 2001.
[10] L. L. Yin, C. K. Keng, and G. Tan, “2.5D/3D device package level defect localization with the use of multiple curve tracings and repeated thermal emission analyses,” in Proc. IEEE 22nd IPFA, Jun. 2015, pp. 287-290.
[11] L. Chengyan, Q. Fei, and B. Zhaowei, “Non-destructive testing for defects in electronic package based on Infrared Thermography,” in Proc. 14th ICEPT, Aug. 2013, pp. 865-869.
[12] F. Novak, B. Hvala, and S. Klav, ”On analog signature analysis,” in Proc. IEEE Design, Automation and Test in Europe Conference and Exhibition, Mar. 1999, pp. 249-253.
[13] B. Zheng, C. Hunat, W. Yuan, N. Suthiwongsunthorn, and S. Chungpaiboonpatana, “Failure isolation for advanced packages using time-domain reflectometry,” in Proc. IEEE 13th EPTC, Dec. 2011, pp. 699-704.
[14] S. Pappalardo, D. Caccialanza, and Z. Mdsarip, “Package level failure analysis: New techniques and new instruments for better results,” in Proc. IEEE 2nd ASQED, Aug. 2010, pp. 84-88.
[15] W. Yuan, W. Zhu, P. Win, C. K. Wang, H. B. Tan, and A. Y. S. Sun, “Packaging Failure Isolation with Time-Domain Reflectometry (TDR) for Advanced BGA Packages,” in Proc. IEEE 2007 8th EPTC, Aug. 2007, pp. 1-5.
[16] L. Cao, H. B. Chong, J. M. Chin, and R. N. Master, “Non-destructive analysis on flip chip package with TDR (time domain reflectometry) and SQUID (superconducting quantum interference device,” in Proc. IEEE 4th EPTC, Dec. 2002, pp. 50-55.
[17] F. Chao, L. Xiaomin and J. Kow, ”3D package failure analysis challenge and solution,” 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC), 2015, pp. 1-4.
[18] D. H. Jung et al., ”Through Silicon Via (TSV) Defect Modeling, Measurement,
and Analysis,” IEEE Transactions on Components, Packaging and Manufacturing
Technology, vol. 7, no. 1, Jan. 2017, pp. 138-152.
[19] Y. Chen, N. Lin, and P. Lai, “Three-dimensional X-Ray laminography as a tool for detection and characterization of package on package(PoP) defects,” in Proc. IEEE 2014 10th ICRMS), Aug. 2014, pp. 275-278.
[20] F. Novak, B. Hvala, and S. Klav, “On analog signature analysis,” in Proc. IEEE Design, Automation and Test in Europe Conference and Exhibition, Mar. 1999, pp. 249-253.
[21] Z. Yang, Z. Guangyu, S. Yonghong, W. Wei, and G. Xuerong, “Test Parameters Optimization Based on Newton-Gaussian Method in Analog Signature Analysis,” in
Proc. IEEE 15th International Conference on Measuring Technology and Mechatronics Automation, Jan. 2013, pp. 1120-1124.
[22] M. K. Chen, C. C. Tai, Y. J. Huang, and I. C. Wu, “Failure analysis of BGA package by a TDR approach,” in Proc. IEEE Proceedings of the 4th International Symposium on Electronic Materials and Packaging, Dec. 2002, pp. 112-116.
[23] M. Engl, K. Schiller, W. Eurskens, and R. Weigel, “High resolution time domain and frequency domain package characterization up to 65 GHz,” in Proc. IEEE 56th ECTC, Dec. 2006, pp. 1274-1280.
[24] M. Engl, W. Eurskens, and R. Weigel, “Comparison of time domain package characterization techniques using TDR and VNA,” in Proc. IEEE Proceedings of 6th
EPTC, Dec. 2004, pp. 490-495.
[25] A. Rumiantsev and N. Ridler, “VNA calibration,” IEEE Microwave Magazine, vol. 9, no. 3, pp. 86-99, Jan. 2008.
[26] Y. Eo and W. R. Eisenstadt, “High-speed VLSI interconnect modeling based on sparameter measurements ,” IEEE Trans. Comp. Hybrids, Manufact. Technol., vol.
16, pp. 555-562, 1993.
[27] G. Hariharan et al., “Reliability Evaluations on 3D IC Package beyond JEDEC,” 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 1517-1522.
[28] 蕭宇軒,中華民國一百零七年六月“A Non-Destructive RF Signature Measurement
Technique for IC Package Electri-cal Failure Analysis,”國立雲林科技大學電子工
程系碩士論文.
[29] 吳 亦 智,中 華 民 國 九 十 三 年 六 月“The Study of Electrical Character and Fault Model for SoC Package,”義守大學電子工程系碩士論文.
[30] 洪藜月,中華民國八十九年六月“Measurement and Simulation on Electrical Characteristics of Electronic Packages,”國立雲林科技大學電子與資訊工程所碩士論
文.
[31] 宜 特 科 技 股 份 有 限 公 司,“IC 開 蓋 去 除 封 膠(Decap)” 取自:https://www.istgroup.com/tw/service/ic-decap/
[32] 維 基 百 科,中 華 民 國 一 百 零 七 年 九 月“Network analyzer(electrical)” 取
自:https://en.wikipedia.org/wiki/Network analyzer (electrical)
[33] 太 克 科 技 股 份 有 限 公 司,中 華 民 國 一 百 零 六 年 三 月“VNA 基 礎 介 紹” 取自:https://download.tek.com/document/%85T 60918 0 Tek VNA PR 05.pdf.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top