臺灣博碩士論文加值系統

半導體的發展在幾十年來遵循摩爾定律下不斷提高電路密度，製程上的微縮(more Moore)越來越困難；所以業界朝另一條more than Moore路線發展，以達到異質整合及3D堆疊的目的，其中矽貫孔(Through Silicon Via, TSV)是能使晶片與晶片垂直連接的關鍵技術，利用導孔內金屬的垂直相連，可以達到尺寸縮小、3D堆疊及異質整合的目的。然而TSV技術也面臨到因材料間熱膨脹係數所產生的挑戰，在高溫TSV製程下，由於不同材料的熱膨脹係數不匹配而產生熱應力，從而發生TSV銅凸與脫層等結構問題。從過去的研究可以發現除了結構問題，也有熱應力對矽晶格產生的壓阻效應，使載子移動率上升而使元件失效形成排除區(Keep Out Zone, KOZ)，影響元件之性能及可靠度。
本研究主要目的為了解TSV各參數因子在熱製程下對應力分佈及載子移動率影響。透過有限元素法，對TSV進行模擬並分別計算其對n-MOS與p-MOS的影響。本研究藉由調整TSV直徑、深寬比、間距直徑比、排列角度幾何尺寸及製程溫度來模擬不同條件之下的應力，通過壓阻效應公式，計算並分析MOS於矽晶格方向[100]與[110]時，其載子移動率的變化趨勢與排除區的範圍變化。最後透過田口方法進行數據及變異分析，探討不同因子對載子移動率之影響程度，並對陣列式TSV提出優化設計，使載子移動率最大值減少約16~26%，以縮小排除區影響範圍，使晶片使用面積增加、尺寸更輕薄短小。

The development of semiconductors has followed Moore's law for decades to increase the circuit density. The process of more Moore is becoming more challenging. Therefore, moving towards more than Moore is an alternative for which through silicon via (TSV) is a key technology to directly connect wafers together vertically, enabling heterogeneous integration by 3D stacking. By utilizing vertically connected metal vias, the package size can be reduced while the device function can be improved. However, because of mismatch of the coefficients of thermal expansion (CTE) among the TSV materials, reliability issues such as delamination could occur due to thermal stresses at high temperature. Moreover, thermal stresses could induce piezoresistive effect on the silicon lattice and affect carrier mobilities which restrict the densification of TSVs in terms of keep-out-zones (KOZs), in addition to reliability concerns..
The main objective of this study is to reveal the effect of TSV parameters on stress distribution and carrier mobility under thermal strains by finite element numerical simulations via Taguchi method for [100] and [110] n-MOS and p-MOS semiconductors. The parameters investigated are the TSV diameter, TSV depth-to-width ratio, TSV pitch-to-diameter ratio, arrangement angle, and process temperature.
The results show that the array angle is the most influential factor, followed by the temperature, while the depth the least. Through optimization by Taguchi method, the maximum carrier mobility values of [100]p-MOS, [100]n-MOS, [110]n-MOS, and [110]p-MOS are reduced by 18.54%, 16.75%, 21.7%, and 26.52%, respectively, allowing better utilization of wafer area.

摘要 I
EXTENDED ABSTRACT II
誌謝 VIII
目錄 IX
表目錄 XI
圖目錄 XIII
符號說明 XVI
第一章 緒論 1
1.1 前言 1
1.1.1 摩爾定律 1
1.1.2 晶片封裝世代發展 1
1.2 研究動機 4
1.3 研究概念 5
1.4 文獻回顧 5
1.5 論文架構 11
第二章 技術背景概述 12
2.1 TSV概述 12
2.1.1 TSV技術與結構 12
2.1.2 TSV製程概述 13
2.1.3 TSV參數因子 16
2.2 單晶矽之壓阻效應 17
2.3熱分析模擬 18
2.3.1 熱分析原理 18
2.3.2 分析軟體介紹 19
2.3.3 熱-結構耦合分析原理 19
2.4田口方法介紹 20
2.4.1直交表 20
2.4.2信號雜訊比 20
2.4.3因子反應分析 21
2.4.4變異分析 21
第三章 研究方法與模擬設置 24
3.1 有限元素模擬規劃 24
3.2 有限元素模擬設定 24
3.2.1 TSV材料性質 24
3.2.2 有限元素模型 26
3.2.3建立網格 28
3.2.4網格歪斜指標 28
3.2.5定義邊界條件 29
3.2.6有限元素模擬 30
第四章 結果與討論 31
4.1矽晶格材料性質比較 31
4.2 排除區定義 34
4.3 第一階段模擬 36
4.3.1 一次一因子模擬設定 36
4.3.2 一次一因子模擬結果 37
4.4 第二階段模擬 52
4.4.1 田口方法模擬設計 52
4.4.2 田口方法模擬結果 54
第五章 結論與建議 67
5.1 結論 67
5.2 建議 68
參考文獻 69

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