臺灣博碩士論文加值系統

隨著半導體產業的高科技高速發展，在車用電子方面，駕駛油電混合動力或電動汽車的意識逐漸提升。 與燃油車相比，車輛更平穩、更安靜，質量和可靠性不遜色於燃油車。 未來，如果能克服車用電池的不確定性，將有機會直接替代燃油車。高功率元器件在汽車電子中扮演著非常重要的角色。在本研究中，討論並介紹了各種 IGBT 結構。 為每個矽材料元件結構提供了二維模擬結構提供討論和分析。 如前所述，可以通過調整IGBT內部結構的參數，實現開關損耗、導通電壓和崩潰電壓等之間的平衡。

同時，為了進行量子計算，cryo-CMOS 一直是一個很有前途的選擇，它可以在 mK 狀態下連接量子處理器和室溫下的外部基本計算處理元件。 Cryo-CMOS 執行量子信號的控制和讀出。 由於冷卻系統和佈線的限制，cryo-CMOS 建議工作在 4K 或更低，而 4K 是我們研究的目標溫度。 但當元件工作溫度低於 150 K 時，矽材料中的摻雜原子會發生凍結。 我們想詳細瞭解不完全電離模型的前後對比和發現。 希望能給大家提供更準確的低溫模擬方法。

在我的研究中，我使用TCAD 中的SDE建立二維結構。使用SDevice完成元件的模擬電性分析。

With the rapid development of high technology in the semiconductor industry, in terms of automotive electronics, the awareness of driving hybrid or electric vehicles is gradually increasing. Compared with fuel vehicles, electric vehicles are smoother and quieter, and their quality and reliability are not inferior to fuel vehicles. In the future, if the uncertainty of vehicle batteries can be overcome, there will be opportunities to directly replace fuel vehicles. High power components play a very important role in automotive electronics. The methodology for designing the internal structure of the insulated-gate bipolar transistor (IGBT) is presented. In this research various IGBT structures were discussed and introduced. The two-dimensional structures are provided for each of the primary silicon device structures to discuss and learn. As described, the parameters of the internal structure of IGBT can be adjusted to achieve a trade-off between the turn-off switching losses, the on-state voltage drop and breakdown voltage etc.... In the case of the IGBT structure, this can be accomplished by adding additional designs (the buffer layer, field stop layer, carrier storage layer etc....) to change the thickness of doping concentration and position. The choice between these approaches depends upon the voltage rating of the device, the available process technology, and the know-how developed by each IGBT manufacturer. To realize quantum computing, cryo-CMOS has been a promising option, interfacing a quantum processor at mK-regime and an external classical computer at room temperature. Cryo-CMOS performs control and readout of the quantum signal. Due to the limited cooling power and the wiring, cryo-CMOS is proposed to work at 4 K or lower, and 4 K is the temperature that we are targeting in our research. When the device operation temperature is lower than 150 K, dopant freeze-out in Si-based devices will occur. We would like to explain in detail the before and after comparison and discovery of the incomplete ionization model. I hope to provide everyone with a more accurate low temperature simulation method. In my research, I use the Sentaurus Structure Editor (SDE) in Technology Computer Aided Design (TCAD) to create a two-dimensional structure. Sentaurus Device (SDevice) will be utilized to simulate electrical analysis.

摘要 I
Abstract II
致謝 III
Contnets IV
Table captions VIII
Figure captions IX
Chapter 1. 1
1.1. Nonpunch Through Insulated Gate Bipolar Transistor (Vertical). 1
1.1.1. Electrical Characteristic 3
 Forward Blocking 3
 Reverse Blocking 3
 Forward Conduction (On-state) 3
 Parasitic Thyristor Latch-Up 4
1.2. Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) 5
1.2.1. N-buffer layer 5
1.2.2. Field-Stop layer 5
1.2.3. Electrical Characteristic 6
 Forward Blocking 6
 Reverse Conduction 6
 Forward Conduction 6
1.3. Injection-Enhanced Insulated Gate Bipolar Transistor 7
1.3.1. Carrier Storage Layer 7
1.3.2. Trench gate Technology 7
1.4. Lateral Insulated Gate Bipolar Transistor 8
1.5. Reverse-Conducting Insulated Gate Bipolar Transistor 9
1.5.1. Snapback Effect 10
1.6. Effect of Temperature Extrinsic Semiconductors. 10
1.7. Electrical Characteristic of Thyristor 12
1.7.1. Structure 12
1.7.2. Electrical Characteristic 13
 Region (0)-(1): The forward blocking (off-state) 13
 Region (1)-(2): The negative-resistance region 13
 Region (2)-(3): The forward conduction (on-state) 13
 Region (0)-(4): The Reverse blocking 14
 Region (4)-(5): The reverse-breakdown 14
1.8. The Latch-up of the Parasitic Thyristor in a CMOS. 16
1.9. Motivation 18
Chapter 2. TCAD Simulation 19
2.1. Introduction to Synopsys Sentaurus TCAD 19
2.2. Sentaurus Device Editor Simulation 19
2.3. Sentaurus Device Simulation 20
2.3.1. Transport Models 20
 Drift-Diffusion Model 20
2.3.2. Fermi Statistics 21
2.3.3. Effective intrinsic Model 22
2.3.4. Mobility Model 22
2.3.5. Generation–Recombination 22
2.3.6. Incomplete Ionization Model 23
2.3.7. Avalanche Breakdown 24
2.4. Sentaurus Device: Physics Section 25
2.4.1. For Lateral Reverse-Conducting Insulated Gate Bipolar Transistor. 25
2.4.2. For Latch-up Behavior of the Parasitic Thyristor in CMOS at Low Temperatures. 26
Chapter 3. Lateral Reverse-Conducting Insulated Gate Bipolar Transistor. 27
3.1. Simulation Setting 27
3.1.1. Device Structure. 28
3.2. Results and Analysis--Snapback effect (1) 30
 L-RC-IGBT with n-buffer layer: 30
 L-RC-IGBT with n-buffer layer and insulated trench (on the left side of the collector): 31
 L-RC-IGBT with n-buffer layer and insulated trench (in the middle of the collector): 31
3.3. Results and Analysis----Snapback effect(2) 34
 L-RC-IGBT with n-buffer layer and insulated trench on the left side of the collector: 34
 L-RC-IGBT with n-buffer layer and insulated trench in the middle of the collector: 35
3.4. Results and Analysis--Breakdown 36
Chapter 4. Latch-up Behavior of the Parasitic Thyristor in CMOS Working at Low Temperatures. 41
4.1. Simulation Setting 42
4.1.1. Device Structure. 42
4.2. SDevice Setup 43
 Step1: 44
 Step2: 45
4.3. Results and Analysis. 46
4.3.1. The turn-on IV of parasitic NPN and PNP BJT. 46
4.3.2. The resistance of the well and the substrate. 52
4.3.3. Latch Up effect. 55
4.3.4. Synopsys reply 57
Chapter 5. Conclusion and Future Works 58
5.1. Lateral Reverse-Conducting Insulated Gate Bipolar Transistor. 58
5.1.1. Conclusion 58
5.1.2. Future work 58
5.2. Latch-up Behavior of the Parasitic Thyristor in CMOS Working at Low Temperatures. 59
5.2.1. Conclusion 59
5.2.2. Future works 59
Reference 60
 Reference in chapter1 60
 Reference in chapter2 61
 Reference in chapter3 61
 Reference in chapter4 62
Appendix I 64
 SDE commands about vertical-RC-IGBT 64
 SDE commands about lateral-RC-IGBT 68
 SDE commands about lateral-RCIGBT (insulated trench in the middle of the collector) 72
 SDE commands about lateral-RCIGBT (insulated trench on the left side of the collector) 77
 SDE commands about cryo-CMOS latch-up 81
Appendix II 84
 SDevice commands for IGBT 84
 SDevice commands for cryo-CMOS latch-up. 86
Appendix III 90
 Parameter commands file for the incomplete ionization (i.i) model 90

Reference in chapter1
[1]T. Terashima and J. Moritani, "High speed lateral-IGBT with a passive gate," Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005., 2005, pp. 91-94, doi: 10.1109/ISPSD.2005.1487958.
[2]I. M. Mackintosh, "The Electrical Characteristics of Silicon P-N-P-N Triodes," in Proceedings of the IRE, vol. 46, no. 6, pp. 1229-1235, June 1958, doi: 10.1109/JRPROC.1958.286908.
[3]Chang, Z., Zhu, X., & Inuishi, M. (2019). Backside layout design of Snapback-free RCIGBT with multiple-cell. Lecture Notes in Engineering and Computer Science, 2239, 299-303.
[4]H. -W. Tsai and M. -D. Ker, "Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits," 2015 European Conference on Circuit Theory and Design (ECCTD), 2015, pp. 1-4, doi: 10.1109/ECCTD.2015.7300129.
[5]Hargrove, M. J., et al. "Latchup in CMOS technology." 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No. 98CH36173). IEEE, 1998.
[6]C. Chen and M. Ker, "Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $mu$ m CMOS Technology," in IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 445-451, June 2019, doi: 10.1109/TDMR.2019.2916721.
[7]Jong-Mun Park 2004-10-28, “RESURF (Reduced Surface Field) technology”.
[8]A. Al Youssef, L. Artola, S. Ducret, G. Hubert and F. Perrier, "Investigation of Electrical Latchup and SEL Mechanisms at Low Temperature for Applications Down to 50 K," in IEEE Transactions on Nuclear Science, vol. 64, no. 8, pp. 2089-2097, Aug. 2017, doi: 10.1109/TNS.2017.2726684.
Sajana m. (2018, September 15). Thyristor – Working, VI Characteristics, Types, Applications, Advantage & Disadvantage. Https://Electricalfundablog.Com. https://electricalfundablog.com/thyristor-working-vi-characteristics/
[9]Ming-Dou Ker and Wen-Yu Lo, "Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology," in IEEE Transactions on Semiconductor Manufacturing, vol. 16, no. 2, pp. 319-334, May 2003, doi: 10.1109/TSM.2003.811885.
Reference in chapter2
[1]SentaurusTM Device User Guide, Synopsys, Version U-2022.12.
Reference in chapter3
[1]H. Meng, J. Chen, F. X. C. Jiang and X. Lin, "A low loss SOI lateral trench IGBT and superjunction device with insulated trench barrier," 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, 2014, pp. 1-3, doi: 10.1109/ICSICT.2014.7021541.
[2]M. Antoniou, F. Udrea, F. Bauer and I. Nistor, "A new way to alleviate the RC IGBT snapback phenomenon: The Super Junction solution," 2010 22nd International Symposium on Power Semiconductor Devices & IC's (ISPSD), Hiroshima, Japan, 2010, pp. 153-156.
[3]Juhyun Oh, Dae Hwan Chun, Reum Oh and Hyun Soo Kim, "A snap-back suppressed shorted-anode lateral trench insulated gate bipolar transistor (LTIGBT) with insulated trench collector," 2011 IEEE International Symposium on Industrial Electronics, Gdansk, 2011, pp. 1367-1370, doi: 10.1109/ISIE.2011.5984358.
[4]Kyoung, Sinsu et al. “Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics.” Solid-state Electronics 140 (2017): 23-28.
[5]Z. Chang, X. Yang, X. Hou and H. Tang, "Suppression Strategy of Snapback Effect for Multi-Cell RC-IGBT," 2020 IEEE 9th International Power Electronics and Motion Control Conference (IPEMC2020-ECCE Asia), Nanjing, China, 2020, pp. 2135-2140, doi: 10.1109/IPEMC-ECCEAsia48364.2020.9368035.
[6]L. Zhang et al., "Optimization of VCE Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF," in IEEE Transactions on Electron Devices, vol. 65, no. 9, pp. 3862-3868, Sept. 2018, doi: 10.1109/TED.2018.2857838.
[7]L. Sun, B. Duan, Y. Wang and Y. Yang, "Fast-Switching Lateral IGBT with Trench/Planar Gate and Integrated Schottky Barrier Diode (SBD)," 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, 2019, pp. 379-382, doi: 10.1109/ISPSD.2019.8757596.
[8]H. Hu, H. Huang and X. B. Chen, "A Novel Diode-Clamped Carrier-Stored SOI Lateral Superjunction IGBT with Ultralow Turn-off Loss and Saturation Current," 2019 IEEE 13th International Conference on Power Electronics and Drive Systems (PEDS), Toulouse, France, 2019, pp. 1-4, doi: 10.1109/PEDS44367.2019.8998773.
[9]G. Deng et al., "A snapback-free RC-IGBT with Alternating N/P buffers," 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017, pp. 127-130, doi: 10.23919/ISPSD.2017.7988943.
[10]M. Watanabe et al., "Accurate TCAD simulation of trench-gate IGBTs and its application to prediction of carrier lifetime requirements for future scaled devices," 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Chengdu, China, 2021, pp. 1-3, doi: 10.1109/EDTM50988.2021.9420922.
[11]I. Deviny et al., "A novel 1700V RET-IGBT (recessed emitter trench IGBT) shows record low VCE(ON), enhanced current handling capability and short circuit robustness," 2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), Sapporo, Japan, 2017, pp. 147-150, doi: 10.23919/ISPSD.2017.7988932.
[12]W. Zhang, Y. Zhu, S. Lu, X. Tian and Y. Teng, "Increase of the Reliability of the Junction Terminations of Reverse-Conducting Insulated Gate Bipolar Transistor by Appropriate Backside Layout Design," in IEEE Electron Device Letters, vol. 35, no. 12, pp. 1281-1283, Dec. 2014, doi: 10.1109/LED.2014.2364301.
[13]K. Ma, W. Zhang and W. T. Ng, "Novel Low Turn-Off Loss Trench-Gate FS-IGBT With a Hybrid p+/n Collector Structure," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 677-681, 2019, doi: 10.1109/JEDS.2019.2918146.
Reference in chapter4
[1]E. Charbon et al., "Cryo-CMOS for quantum computing," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 13.5.1-13.5.4, doi: 10.1109/IEDM.2016.7838410.
[2]H. Y. Wong, "Calibrated Si Mobility and Incomplete Ionization Models with Field Dependent Ionization Energy for Cryogenic Simulations," 2020 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kobe, Japan, 2020, pp. 193-196, doi: 10.23919/SISPAD49475.2020.9241599.
[3]Foty, Daniel. “Impurity ionization in MOSFETs at very low temperatures.” Cryogenics 30 (1990): 1056-1063.
[4]Gupta, Rajesh K., Isami Sakai, and Chenming Hu. "Effects of substrate resistance on CMOS latchup holding voltages." IEEE transactions on electron devices 34.11 (1987): 2309-2316.
[5]Al Youssef, A. et al. “Investigation of Electrical Latchup and SEL Mechanisms at Low Temperature for Applications Down to 50 K.” IEEE Transactions on Nuclear Science 64 (2017): 2089-2097.
[6]R. K. Gupta, I. Sakai and Chenming Hu, "Effects of substrate resistance on CMOS latchup holding voltages," in IEEE Transactions on Electron Devices, vol. 34, no. 11, pp. 2309-2316, Nov. 1987, doi: 10.1109/T-ED.1987.23237.